On Mon, Dec 19, 2016 at 01:50:15AM +0000, Andre Przywara wrote: > The ARMv8 capable Allwinner A64 SoC comes out of reset in AArch32 mode. > To run AArch64 code, we have to trigger a warm reset via the RMR register, > which proceeds with code execution at the address stored in the RVBAR > register. > If the bootable payload in the FIT image is using a different > architecture than the SPL has been compiled for, enter it via this said > RMR switch mechanism, by writing the entry point address into the MMIO > mapped, writable version of the RVBAR register. > Then the warm reset is triggered via a system register write. > If the payload architecture is the same as the SPL, we use the normal > branch as usual. > > Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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