-----Original Message-----
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Thursday, October 08, 2009 7:33 PM
To: Dudhat Dipen-B09055
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v2 3/3] ppc/p1_p1_RDB: DDR Relocation
support for NAND/SD/eSPI Boot
[snip]
> --- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
> +++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
> @@ -39,6 +39,60 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#if !defined(CONFIG_L2_RELOC)
> +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
> +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
> +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
> +#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type =
> DDR2*/
> +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
> +
> +#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
> +#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
> +#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
> +#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
> +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
> +#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
> +
> +#define udelay(x) {int i, j; for (i = 0; i < x; i++) for (j = 0; j
> < 10000; j++); }
> +
> +void initsdram(void)
> +{
> +
> + volatile ccsr_ddr_t *ddr= (ccsr_ddr_t
*)CONFIG_SYS_MPC85xx_DDR_ADDR;
> + int d_init, dbw;
> + volatile ccsr_gpio_t *pgpio = (void *)
> (CONFIG_SYS_MPC85xx_GPIO_ADDR);
> + unsigned int ddr_size;
> + sys_info_t sysinfo;
> + phys_size_t dram_size = 0;
> +
> + set_next_law(0,LAW_SIZE_1G , LAW_TRGT_IF_DDR_1);
Can we not use fsl_ddr_set_memctl_regs()? If not these should be
using out_be32()
Why can't we use set_next_law / set_law function here???
I mean at the end they are using out_be32() for setting up LAW
registers..
- Dipen
> +
> + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
> + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
> + ddr->cs0_config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2;
> +
> + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667;
> + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667;
> + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667;
> + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667;
> + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1_667;
> + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667;
> + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL_667;
> + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667;
> + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
> + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2;
> +
> + asm("sync;isync");
> +
> + udelay(500);
> +
> + ddr->sdram_cfg |= 0x80000000;
> +
> +}
> +#endif
> +
> void board_init_f(ulong bootflag)
> {
> uint plat_ratio, bus_clk, sys_clk;
> @@ -69,6 +123,11 @@ void board_init_f(ulong bootflag)
>
> puts("\nNAND boot... ");
>
> +#ifndef CONFIG_L2_RELOC
> + /* board specific DDR initialization */
> + initsdram();
> +#endif
> +
> /* copy code to DDR and jump to it - this should not return */
> /* NOTE - code has to be copied out of NAND buffer before
> * other blocks can be read.
> --
> 1.5.6.3
>
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