The SPL is unable to load u-boot because the DDR2 is not configured.
Configure the DDR2.
Signed-off-by: Fabien Parent <fpar...@baylibre.com>
---
v2 -> v3
* Use new Kconfig option SYS_DA850_DDR_INIT instead of defining it in
the config header file
v1 -> v2
* New patch
---
arch/arm/mach-davinci/Kconfig | 1 +
include/configs/omapl138_lcdk.h | 41 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 067b6c3..c593dad 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -23,6 +23,7 @@ config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SUPPORT_SPL
select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_CALIMAIN
bool "Calimain board"
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 854fc47..9db9cea 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -79,6 +79,47 @@
#define CONFIG_SYS_DA850_PLL1_PLLM 21
/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+ DV_DDR_PHY_EXT_STRBEN | \
+ (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
+ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
+ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
+ (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
+ (4 << DV_DDR_SDCR_CL_SHIFT) | \
+ (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
+ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
+ (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
+ (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
+ (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
+ (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
+ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
+ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
+ (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
+ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
+ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
+#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+
+/*
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_SERIAL
--
2.10.2
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
