The SPL is not able to boot properly because the PLL0 is not
configured. Configure it.

Signed-off-by: Fabien Parent <fpar...@baylibre.com>
---

V1 -> V2
 * New patch

---
 include/configs/omapl138_lcdk.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 854fc47..ce3a8f4 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -30,6 +30,7 @@
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK            clk_get(DAVINCI_AUXCLK_CLKID)
 #define CONFIG_SYS_HZ                  1000
+#define CONFIG_SYS_DA850_PLL_INIT
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_TEXT_BASE           0xc1080000
 
-- 
2.10.2

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