On 11/16/2016 01:23 AM, Wenbin Song wrote: > Hi: york > > Best Regards > Wenbin Song > > >> -----Original Message----- >> From: york sun >> Sent: Tuesday, November 15, 2016 5:24 AM >> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net; >> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de >> Subject: Re: [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC >> node >> >> On 10/31/2016 08:35 PM, Wenbin song wrote: >>> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K >>> alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] >>> is used to choose which offset will be used. If GIC_ADDR_BIT bit is >>> set, 4K alignment is used, or else 64K alignment is used. The rev1.0 >>> silicon only supports the CIG offset with 4K alignment. >> >> Wenbin, >> >> According to your patch and your explanation, the rev 1 SoC supports 4K >> alignment only. The rev 1.1 and newer SoC supports both 4K and 64K. If you >> don't do anything in PBI, the default is 64K. > > [] yes. You are correct .
I would prefer it has 4K alignment if you do nothing in PBI. But I guess it is too late to change the hardware. > > Does this 64k alignment apply to >> any other SoCs? >> > [] This patch only apply to ls1043a. and the other SOCs only support one > kind of alignment style. For example, ls1046a align with 64k, ls1012a align > with 4k. In this case, you patch is OK. You can add full SVR check if a future SoC needs the same fix. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
