On Fri, Oct 28, 2016 at 12:01:43PM +0530, Keerthy wrote: > While we setup the mmu initially we mark set_section_dcache with > DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro > is rightly defined with TTB_SECT_XN_MASK set so as to mark all the > 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with > DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which > keeps all the regions execute okay and this leads to random speculative > fetches in random memory regions which was eventually caught by kernel > omap-l3-noc driver. > > Fix this to mark the regions as XN by default. > > Signed-off-by: Keerthy <j-keer...@ti.com> > --- > arch/arm/include/asm/system.h | 2 +- > arch/arm/lib/cache-cp15.c | 5 +++++ > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h > index b928bd8..2f430ad 100644 > --- a/arch/arm/include/asm/system.h > +++ b/arch/arm/include/asm/system.h > @@ -329,7 +329,7 @@ static inline void set_dacr(unsigned int val) > > /* options available for data cache on each page */ > enum dcache_option { > - DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0), > + DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK, > DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), > DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), > DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3), > diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c > index 70e94f0..4d9903e 100644 > --- a/arch/arm/lib/cache-cp15.c > +++ b/arch/arm/lib/cache-cp15.c > @@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, > size_t size, > > end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; > start = start >> MMU_SECTION_SHIFT; > +#ifdef CONFIG_ARMV7_LPAE > + debug("%s: start=%pa, size=%zu, option=%llu\n", __func__, &start, size, > + option); > +#else > debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size, > option); > +#endif
Does it really make sense to be printing option in decimal rather than hex here? -- Tom
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