Hi Stefano, Ping..
Thanks, Peng. On Sat, Oct 08, 2016 at 04:58:29PM +0800, Peng Fan wrote: >From: "Ye.Li" <ye...@nxp.com> > >Need to gate ENET clock when switching to a new clock parent, because >the mux is not glitchless. > >Signed-off-by: Peng Fan <peng....@nxp.com> >Signed-off-by: Ye.Li <ye...@nxp.com> >Cc: Stefano Babic <sba...@denx.de> >--- > arch/arm/cpu/armv7/mx6/clock.c | 5 +++++ > 1 file changed, 5 insertions(+) > >diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c >index ae3143c..96fbd81 100644 >--- a/arch/arm/cpu/armv7/mx6/clock.c >+++ b/arch/arm/cpu/armv7/mx6/clock.c >@@ -881,6 +881,11 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq >freq) > writel(reg, &anatop->pll_enet); > > #ifdef CONFIG_MX6SX >+ /* Disable enet system clcok before switching clock parent */ >+ reg = readl(&imx_ccm->CCGR3); >+ reg &= ~MXC_CCM_CCGR3_ENET_MASK; >+ writel(reg, &imx_ccm->CCGR3); >+ > /* > * Set enet ahb clock to 200MHz > * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB >-- >2.6.2 > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
