On 10/13/2016 10:33 AM, Chin Liang See wrote:
> Add SPL support for Stratix 10 SoC development kit
>
> Signed-off-by: Chin Liang See <cl...@altera.com>
> Cc: Marek Vasut <ma...@denx.de>
> Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> Cc: Ley Foon Tan <lf...@altera.com>
> Cc: Tien Fong Chee <tfc...@altera.com>
> ---
> arch/arm/mach-socfpga/Makefile | 13 ++++++++-----
> arch/arm/mach-socfpga/spl.c | 13 ++++++++++++-
> 2 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 5038919..2b00c8c 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -8,17 +8,20 @@
> #
>
> obj-y += misc.o timer.o reset_manager.o clock_manager.o board.o
> -
> -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> -
> obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += mmu-arm64.o
>
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o
> +endif
> +
> +ifdef CONFIG_TARGET_SOCFPGA_GEN5
> # QTS-generated config file wrappers
> -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
> - fpga_manager.o system_manager.o
> +obj-y += scan_manager.o wrap_pll_config.o fpga_manager.o
> system_manager.o
> obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
> wrap_sdram_config.o
> CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
> CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
> CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
> CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
> +endif
> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
> index fec4c7a..b514a01 100644
> --- a/arch/arm/mach-socfpga/spl.c
> +++ b/arch/arm/mach-socfpga/spl.c
It seems like the only thing which happens in the spl.c for S10 is it
calls spl_console_init(). In that case, just split the spl into gen5 one
and S10 one instead of polluting it with ifdefs.
> @@ -22,6 +22,7 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> static struct pl310_regs *const pl310 =
> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> static struct scu_registers *scu_regs =
> @@ -30,9 +31,11 @@ static struct nic301_registers *nic301_regs =
> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> static struct socfpga_system_manager *sysmgr_regs =
> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +#endif
>
> u32 spl_boot_device(void)
> {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> const u32 bsel = readl(&sysmgr_regs->bootinfo);
>
> switch (bsel & 0x7) {
> @@ -55,6 +58,9 @@ u32 spl_boot_device(void)
> printf("Invalid boot device (bsel=%08x)!\n", bsel);
> hang();
> }
> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> + return BOOT_DEVICE_MMC1;
> +#endif
> }
>
> #ifdef CONFIG_SPL_MMC_SUPPORT
> @@ -68,6 +74,7 @@ u32 spl_boot_mode(const u32 boot_device)
> }
> #endif
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> static void socfpga_nic301_slave_ns(void)
> {
> writel(0x1, &nic301_regs->lwhps2fpgaregs);
> @@ -77,9 +84,11 @@ static void socfpga_nic301_slave_ns(void)
> writel(0x1, &nic301_regs->ocram);
> writel(0x1, &nic301_regs->sdrdata);
> }
> +#endif
>
> void board_init_f(ulong dummy)
> {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
> const struct cm_config *cm_default_cfg = cm_get_default_config();
> #endif
> @@ -152,10 +161,11 @@ void board_init_f(ulong dummy)
> debug("Unfreezing/Thaw all I/O banks\n");
> /* unfreeze / thaw all IO banks */
> sys_mgr_frzctrl_thaw_req();
> -
> +#endif
> /* enable console uart printing */
> preloader_console_init();
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> if (sdram_mmr_init_full(0xffffffff) != 0) {
> puts("SDRAM init failed.\n");
> hang();
> @@ -181,4 +191,5 @@ void board_init_f(ulong dummy)
>
> /* Configure simple malloc base pointer into RAM. */
> gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
> +#endif
> }
>
--
Best regards,
Marek Vasut
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