Prabhakar, On 09/11/2016 09:20 PM, Zhiqiang Hou wrote: > From: Hou Zhiqiang <zhiqiang....@nxp.com> > > Up to now, there are 3 kinds of SoC under Layerscape Chassis 2, > such as LS1043A, LS1046A and LS1012A. But the clocks tree has a > lot of difference, for instance the IP modules have different > divisors to get clock from Platform PLL. And the core cluster > and platform PLL maybe have different reference clock, such as > LS1012A. Another problem is which clock/PLL should be described > by sys_info->freq_systembus, it is confused in Chissis 2. > > This patch is to map the sys_info->freq_systembus to the Platform > PLL, and handle the different divisor of IP modules separately > between different SoCs. And separate cluster and platform PLL > reference clock. > > Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com> > --- > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 96 > ++++++++++++++++++---- > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + > include/configs/ls1012a_common.h | 6 +- > include/configs/ls1043a_common.h | 2 +- > 4 files changed, 86 insertions(+), 19 deletions(-)
Please review this set. It collides with your patch set. I like Zhiqiang's idea to use platform PLL instead of platform clock. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
