On Wed, Sep 7, 2016 at 3:18 PM, Vignesh R <vigne...@ti.com> wrote: > TI QSPI has four 32 bit data registers which can be used to transfer 16 > bytes of data at once. The register group QSPI_SPI_DATA_REG_3, > QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is > treated as a single 128-bit word for shifting data in and out. The bit > at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out > in case of 128 bit transfer mode. Therefore the first byte to be written > to flash should be at QSPI_SPI_DATA_REG_3[31-25] position. > Instead of writing 1 byte at a time when interacting with SPI NOR flash, > make use of all the four registers so that 16 bytes can be transferred > in one go. > > With this patch, the flash write speed increases from ~250KBs/ to > ~650KB/s on DRA74 EVM. > > Signed-off-by: Vignesh R <vigne...@ti.com> > Reviewed-by: Tom Rini <tr...@konsulko.com>
Reviewed-by: Jagan Teki <jt...@openedev.com> thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
