The CONFIG_SYS_CACHELINE_SIZE is not defined for
some of the platforms due to which buildman iill
fail for these platforms.
Fixing this issue in generic way in Kconfig by
selecting cacheline size based on arm processor type.
This patch is based on linux kernel commit 5637a126
Signed-off-by: Ravi Babu <ravib...@ti.com>
Reviewed-by: Lukasz Majewski <l.majew...@samsung.com>
---
arch/arm/Kconfig | 11 +++++++++++
arch/arm/include/asm/armv7.h | 1 +
arch/arm/include/asm/cache.h | 5 +++++
3 files changed, 17 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef901c..776d3b7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -42,6 +42,17 @@ config CPU_V7
select HAS_VBAR
select HAS_THUMB2
+config ARM_L1_CACHE_SHIFT_6
+ bool
+ default y if CPU_V7
+ help
+ Setting ARM L1 cache line size to 64 Bytes.
+
+config ARM_L1_CACHE_SHIFT
+ int
+ default 6 if ARM_L1_CACHE_SHIFT_6
+ default 5
+
config CPU_V7M
bool
select HAS_THUMB2
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index a20702e..fb3b59b 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -60,6 +60,7 @@
#include <linux/types.h>
#include <asm/io.h>
#include <asm/barriers.h>
+#include <asm/cache.h>
/*
* Workaround for ARM errata # 798870
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 16e65c3..7c57422 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -47,6 +47,11 @@ void dram_bank_mmu_setup(int bank);
* use that value for aligning DMA buffers unless the board config has
specified
* an alternate cache line size.
*/
+#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE (1 << L1_CACHE_SHIFT)
+#endif
+
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
--
1.7.9.5
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