On 08/19/2016 03:13 AM, Sriram Dash wrote:
> Currently the controller by default enables the Receive Detect feature in P3
> mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
> detection in P3 mode.
> Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
> Detect feature is required.
>
> Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
> ---
> drivers/usb/host/xhci-dwc3.c | 5 +++++
> drivers/usb/host/xhci-fsl.c | 7 +++++++
> include/linux/usb/dwc3.h | 2 ++
> 3 files changed, 14 insertions(+)
>
> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
> index 33961cd..adbd9b5 100644
> --- a/drivers/usb/host/xhci-dwc3.c
> +++ b/drivers/usb/host/xhci-dwc3.c
> @@ -97,3 +97,8 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
> setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
> GFLADJ_30MHZ(val));
> }
> +
> +void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val)
> +{
> + setbits_le32(&dwc3_reg->g_usb3pipectl[0], val);
> +}
> diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
> index bdcd4f1..d9dbf1f 100644
> --- a/drivers/usb/host/xhci-fsl.c
> +++ b/drivers/usb/host/xhci-fsl.c
> @@ -74,6 +74,13 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
> /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
> dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
>
> + /*
> + * A-010151: USB controller to configure USB in P2 mode
> + * whenever the Receive Detect feature is required
> + */
> + dwc3_set_rxdetect_power_mode(fsl_xhci->dwc3_reg,
> + DWC3_GUSB3PIPECTL_DISRXDETP3);
> +
Would it be appropriate to gate the code by checking SoC version?
York
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