Adjust POR_B settings on i.MX6ULL according to IC design
team's suggestion:
2'b00 : always PUP100K
2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL
2'b10 : always disable PUP100K
2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting
Signed-off-by: Peng Fan <peng....@nxp.com>
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
Cc: Stefano Babic <sba...@denx.de>
---
arch/arm/cpu/armv7/mx6/soc.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f062d86..c552512 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -366,6 +366,20 @@ int arch_cpu_init(void)
writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
}
+ if (is_mx6ull()) {
+ /*
+ * GPBIT[1:0] is suggested to set to 2'b11:
+ * 2'b00 : always PUP100K
+ * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
+ * 2'b10 : always disable PUP100K
+ * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
+ * register offset is different from i.MX6UL, since
+ * i.MX6UL is fixed by ECO.
+ */
+ writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
+ 0x3, MX6UL_SNVS_LP_BASE_ADDR);
+ }
+
/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
set_preclk_from_osc();
--
2.6.2
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