Hi Lokesh On Tue, Aug 9, 2016 at 12:47 AM, Lokesh Vutla <lokeshvu...@ti.com> wrote: > cpsw tries to flush dcache which is not in the range of PKTSIZE. > Because of this the following warning comes while flushing: > > CACHE: Misaligned operation at range [dffecec0, dffed016] > > Fix it by flushing cache of size PKTSIZE_ALIGN as similar to what is > being done in _cpsw_recv. > > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com> > --- > Changes since v1: > - Use PKTALIGN instead of cache line size > - Need not align start of packet buffer from the network subsystem. > > drivers/net/cpsw.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c > index 2ce4ec6..8ce5716 100644 > --- a/drivers/net/cpsw.c > +++ b/drivers/net/cpsw.c > @@ -907,7 +907,7 @@ static int _cpsw_send(struct cpsw_priv *priv, void > *packet, int length) > int timeout = CPDMA_TIMEOUT; > > flush_dcache_range((unsigned long)packet, > - (unsigned long)packet + length); > + (unsigned long)packet + PKTSIZE_ALIGN);
Technically you are flushing more than needed since you just need to be aligned to the cacheline beyond the size being sent, but you are flushing the maximum packet size every time. That said, it's still going to work and the code is readable. I'm fine with this, but wanted to make sure you knew this is more flushing than needed. Acked-by: Joe Hershberger <joe.hershber...@ni.com> > /* first reap completed packets */ > while (timeout-- && > -- > 2.9.2 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
