Hi Jaehoon,
On Thu, Aug 04, 2016 at 02:32:16PM +0900, Jaehoon Chung wrote:
>Hi Peng,
>
>On 04/26/2016 03:54 PM, Peng Fan wrote:
>> When booting in eMMC fast boot, MMC host does not exit from
>> boot mode after bootrom loading image. So the first command
>> 'CMD0' sent in uboot will pull down the CMD line to low and
>> cause errors.
>>
>> This patch cleans the MMC boot register in "mmc_init" to put the
>> MMC host back to normal mode.
>
>Could you resend the patch-set [1/3 - 3/3] on latest u-boot?
>After that, I will check..
This patch set already merged through York's tree.
Thanks,
Peng.
>
>Best Regards,
>Jaehoon Chung
>
>>
>> Also clear DLL_CTRL delay line settings at USDHC initialization
>> to eliminate the pre-settings from boot rom.
>>
>> Signed-off-by: Peng Fan <van.free...@gmail.com>
>> Cc: Pantelis Antoniou <pa...@antoniou-consulting.com>
>> Cc: York Sun <york....@nxp.com>
>> Cc: Stefano Babic <sba...@denx.de>
>> ---
>> drivers/mmc/fsl_esdhc.c | 38 +++++++++++++++++++++++++++++---------
>> include/fsl_esdhc.h | 6 ++++++
>> 2 files changed, 35 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
>> index 65ecff5..15cd419 100644
>> --- a/drivers/mmc/fsl_esdhc.c
>> +++ b/drivers/mmc/fsl_esdhc.c
>> @@ -57,21 +57,27 @@ struct fsl_esdhc {
>> uint fevt; /* Force event register */
>> uint admaes; /* ADMA error status register */
>> uint adsaddr; /* ADMA system address register */
>> - char reserved2[100]; /* reserved */
>> - uint vendorspec; /* Vendor Specific register */
>> - char reserved3[56]; /* reserved */
>> + char reserved2[4];
>> + uint dllctrl;
>> + uint dllstat;
>> + uint clktunectrlstatus;
>> + char reserved3[84];
>> + uint vendorspec;
>> + uint mmcboot;
>> + uint vendorspec2;
>> + char reserved4[48];
>> uint hostver; /* Host controller version register */
>> - char reserved4[4]; /* reserved */
>> - uint dmaerraddr; /* DMA error address register */
>> char reserved5[4]; /* reserved */
>> - uint dmaerrattr; /* DMA error attribute register */
>> + uint dmaerraddr; /* DMA error address register */
>> char reserved6[4]; /* reserved */
>> + uint dmaerrattr; /* DMA error attribute register */
>> + char reserved7[4]; /* reserved */
>> uint hostcapblt2; /* Host controller capabilities register 2 */
>> - char reserved7[8]; /* reserved */
>> + char reserved8[8]; /* reserved */
>> uint tcr; /* Tuning control register */
>> - char reserved8[28]; /* reserved */
>> + char reserved9[28]; /* reserved */
>> uint sddirctl; /* SD direction control register */
>> - char reserved9[712]; /* reserved */
>> + char reserved10[712];/* reserved */
>> uint scr; /* eSDHC control register */
>> };
>>
>> @@ -618,6 +624,20 @@ static int esdhc_init(struct mmc *mmc)
>> while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
>> udelay(1000);
>>
>> +#if defined(CONFIG_FSL_USDHC)
>> + /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
>> + esdhc_write32(®s->mmcboot, 0x0);
>> + /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
>> + esdhc_write32(®s->mixctrl, 0x0);
>> + esdhc_write32(®s->clktunectrlstatus, 0x0);
>> +
>> + /* Put VEND_SPEC to default value */
>> + esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
>> +
>> + /* Disable DLL_CTRL delay line */
>> + esdhc_write32(®s->dllctrl, 0x0);
>> +#endif
>> +
>> #ifndef ARCH_MXC
>> /* Enable cache snooping */
>> esdhc_write32(®s->scr, 0x00000040);
>> diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
>> index fa760a5..78c67c8 100644
>> --- a/include/fsl_esdhc.h
>> +++ b/include/fsl_esdhc.h
>> @@ -35,6 +35,12 @@
>> #define SYSCTL_RSTC 0x02000000
>> #define SYSCTL_RSTD 0x04000000
>>
>> +#define VENDORSPEC_CKEN 0x00004000
>> +#define VENDORSPEC_PEREN 0x00002000
>> +#define VENDORSPEC_HCKEN 0x00001000
>> +#define VENDORSPEC_IPGEN 0x00000800
>> +#define VENDORSPEC_INIT 0x20007809
>> +
>> #define IRQSTAT 0x0002e030
>> #define IRQSTAT_DMAE (0x10000000)
>> #define IRQSTAT_AC12E (0x01000000)
>>
>
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