Am 27.07.2016 um 12:51 schrieb Zubair Lutfullah Kakakhel: > MIPSfpga is an FPGA based dev platform. > > In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks > > The FPGA dev board used is the Nexys4DDR board by Digilent. > > For more information, check the Readme file in board/imgtec/xilfpga > > Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com> > Reviewed-by: Paul Burton <paul.bur...@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
some nits below
> ---
> arch/mips/Kconfig | 16 ++++++++++
> board/imgtec/xilfpga/Kconfig | 15 +++++++++
> board/imgtec/xilfpga/MAINTAINERS | 6 ++++
> board/imgtec/xilfpga/Makefile | 7 +++++
> board/imgtec/xilfpga/README | 55 ++++++++++++++++++++++++++++++++
> board/imgtec/xilfpga/xilfpga.c | 20 ++++++++++++
> configs/imgtec_xilfpga_defconfig | 25 +++++++++++++++
> include/configs/imgtec_xilfpga.h | 68
> ++++++++++++++++++++++++++++++++++++++++
> 8 files changed, 212 insertions(+)
> create mode 100644 board/imgtec/xilfpga/Kconfig
> create mode 100644 board/imgtec/xilfpga/MAINTAINERS
> create mode 100644 board/imgtec/xilfpga/Makefile
> create mode 100644 board/imgtec/xilfpga/README
> create mode 100644 board/imgtec/xilfpga/xilfpga.c
> create mode 100644 configs/imgtec_xilfpga_defconfig
> create mode 100644 include/configs/imgtec_xilfpga.h
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 21066f0..c81c9ea 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -73,10 +73,26 @@ config MACH_PIC32
> select OF_CONTROL
> select DM
>
> +config TARGET_XILFPGA
> + bool "Support Imagination Xilfpga"
> + select OF_CONTROL
> + select DM
> + select DM_SERIAL
> + select DM_GPIO
> + select DM_ETH
> + select SUPPORTS_LITTLE_ENDIAN
> + select SUPPORTS_CPU_MIPS32_R1
> + select SUPPORTS_CPU_MIPS32_R2
> + select MIPS_L1_CACHE_SHIFT_4
> + select SYS_MIPS_CACHE_INIT_RAM_LOAD
you don't need this option on a microAptiv core and because don't do any
cache initialization in software at all
> + help
> + This supports IMGTEC MIPSfpga platform
> +
> endchoice
>
> source "board/dbau1x00/Kconfig"
> source "board/imgtec/malta/Kconfig"
> +source "board/imgtec/xilfpga/Kconfig"
> source "board/micronas/vct/Kconfig"
> source "board/pb1x00/Kconfig"
> source "board/qemu-mips/Kconfig"
> diff --git a/board/imgtec/xilfpga/Kconfig b/board/imgtec/xilfpga/Kconfig
> new file mode 100644
> index 0000000..b078278
> --- /dev/null
> +++ b/board/imgtec/xilfpga/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_XILFPGA
> +
> +config SYS_BOARD
> + default "xilfpga"
> +
> +config SYS_VENDOR
> + default "imgtec"
> +
> +config SYS_CONFIG_NAME
> + default "imgtec_xilfpga"
> +
> +config SYS_TEXT_BASE
> + default 0x80C00000
> +
> +endif
> diff --git a/board/imgtec/xilfpga/MAINTAINERS
> b/board/imgtec/xilfpga/MAINTAINERS
> new file mode 100644
> index 0000000..aa04532
> --- /dev/null
> +++ b/board/imgtec/xilfpga/MAINTAINERS
> @@ -0,0 +1,6 @@
> +XILFPGA BOARD
> +M: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
> +S: Maintained
> +F: board/imgtec/xilfpga
> +F: include/configs/xilfpga.h
> +F: configs/imgtec_xilfpga_defconfig
> diff --git a/board/imgtec/xilfpga/Makefile b/board/imgtec/xilfpga/Makefile
> new file mode 100644
> index 0000000..9aaf9ce
> --- /dev/null
> +++ b/board/imgtec/xilfpga/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (C) 2016, Imagination Technologies Ltd.
> +# Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +obj-y := xilfpga.o
> diff --git a/board/imgtec/xilfpga/README b/board/imgtec/xilfpga/README
> new file mode 100644
> index 0000000..ac19d48
> --- /dev/null
> +++ b/board/imgtec/xilfpga/README
> @@ -0,0 +1,55 @@
> +/*
> + * Copyright (C) 2016, Imagination Technologies Ltd.
> + *
> + * Zubair Lutfullah Kakakhel, zubair.kakak...@imgtec.com
> + */
> +
> +MIPSfpga
> +=======================================
> +
> +MIPSfpga is an FPGA based development platform by Imagination Technologies
> +As we are dealing with a MIPS core instantiated on an FPGA, specifications
> +are fluid and can be varied in RTL.
> +
> +The example project provided by IMGTEC runs on the Nexys4DDR board by
> +Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
> +the example project and the Nexys4DDR board:
> +
> +- microAptiv UP core m14Kc
> +- 50MHz clock speed
> +- 128Mbyte DDR RAM at 0x0000_0000
> +- 8Kbyte RAM at 0x1000_0000
> +- axi_intc at 0x1020_0000
> +- axi_uart16550 at 0x1040_0000
> +- axi_gpio at 0x1060_0000
> +- axi_i2c at 0x10A0_0000
> +- custom_gpio at 0x10C0_0000
> +- axi_ethernetlite at 0x10E0_0000
> +- 8Kbyte BootRAM at 0x1FC0_0000
> +- 16Mbyte QPI at 0x1D00_0000
> +
> +Boot protocol:
> +--------------
> +
> +The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
> +This is for easy reprogrammibility via JTAG.
just for my understanding: what does "RAM" mean? I would expect a
reprogrammable ROM because this should be a non-volatile memory,
shouldn't it? Or do you always download the BootRAM via JTAG in order to
boot?
> +
> +DDR initialization is already handled by a HW IP block.
> +
> +When the example project bitstream is loaded, the cpu_reset button
> +needs to be pressed.
> +
> +The bootram initializes the cache and axi_uart
> +Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
> +
> +If there is, then that is considered as u-boot. u-boot is copied from
> +0x1D40_0000 to memory and the bootram jumps into u-boot code.
> +
> +At this point, the board is ready to load the Linux kernel + buildroot
> initramfs
> +
> +This can be done in multiple ways:
> +
> +1- JTAG load the binary and jump into it.
> +2- Load kernel stored in the QSPI flash at 0x1D80_0000
> +3- Load uImage via tftp. Ethernet works in u-boot.
> + e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
> diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
> new file mode 100644
> index 0000000..9549e23
> --- /dev/null
> +++ b/board/imgtec/xilfpga/xilfpga.c
> @@ -0,0 +1,20 @@
> +/*
> + * Imagination Technologies MIPSfpga platform code
> + *
> + * Copyright (C) 2016, Imagination Technologies Ltd.
> + *
> + * Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + */
> +
> +#include <common.h>
> +
> +/* initialize the DDR Controller and PHY */
> +phys_size_t initdram(int board_type)
> +{
> + /* MIG IP block is smart and doesn't need SW
> + * to do any init */
> + return 128 * 1024 * 1024; /* in bytes */
is this always fixed to 128 or can you read the size from some hardware
registers? In the first case you should use CONFIG_SYS_SDRAM_SIZE which
you already provide in include/configs/imgtec_xilfpga.h.
> +}
> diff --git a/configs/imgtec_xilfpga_defconfig
> b/configs/imgtec_xilfpga_defconfig
> new file mode 100644
> index 0000000..63f03cd
> --- /dev/null
> +++ b/configs/imgtec_xilfpga_defconfig
> @@ -0,0 +1,25 @@
> +CONFIG_MIPS=y
> +CONFIG_SYS_MALLOC_F_LEN=0x600
> +CONFIG_TARGET_XILFPGA=y
> +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
> +CONFIG_MIPS_BOOT_FDT=y
> +CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
> +CONFIG_BOOTDELAY=5
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="MIPSfpga # "
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_SAVEENV is not set
> +CONFIG_CMD_MEMINFO=y
> +# CONFIG_CMD_FLASH is not set
> +# CONFIG_CMD_FPGA is not set
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_TIME=y
> +CONFIG_OF_EMBED=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_NETCONSOLE=y
> +CONFIG_CLK=y
> +CONFIG_XILINX_EMACLITE=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_CMD_DHRYSTONE=y
> diff --git a/include/configs/imgtec_xilfpga.h
> b/include/configs/imgtec_xilfpga.h
> new file mode 100644
> index 0000000..0a7fe60
> --- /dev/null
> +++ b/include/configs/imgtec_xilfpga.h
> @@ -0,0 +1,68 @@
> +/*
> + * Copyright (C) 2016, Imagination Technologies Ltd.
> + *
> + * Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Imagination Technologies Ltd. MIPSfpga
> + */
> +
> +#ifndef __XILFPGA_CONFIG_H
> +#define __XILFPGA_CONFIG_H
> +
> +/* BootROM + MIG is pretty smart. DDR and Cache initialized */
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +
> +/*--------------------------------------------
> + * CPU configuration
> + */
> +/* CPU Timer rate */
> +#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
> +
> +/* Cache Configuration */
> +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
> +
> +/*----------------------------------------------------------------------
> + * Memory Layout
> + */
> +
> +/* SDRAM Configuration (for final code, data, stack, heap) */
> +#define CONFIG_SYS_SDRAM_BASE 0x80000000
> +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
> +
> +#define CONFIG_SYS_MALLOC_LEN (256 << 10)
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */
> +
> +/*----------------------------------------------------------------------
> + * Commands
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +
> +/*-------------------------------------------------
> + * FLASH configuration
> + */
> +#define CONFIG_SYS_NO_FLASH
> +
> +/*------------------------------------------------------------
> + * Console Configuration
> + */
> +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
> +#define CONFIG_BAUDRATE 115200
> +
> +/* -------------------------------------------------
> + * Environment
> + */
> +#define CONFIG_ENV_IS_NOWHERE 1
> +#define CONFIG_ENV_SIZE 0x4000
> +
> +/* ---------------------------------------------------------------------
> + * Board boot configuration
> + */
> +#define CONFIG_TIMESTAMP /* Print image info with timestamp */
> +
> +#endif /* __XILFPGA_CONFIG_H */
>
--
- Daniel
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