This "commit 429790026021d522d51617217d4b86218cca5750" is wrong.
SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit.
For example, Exynos didn't have CTRL_HISPD. But Highspeed mode
is supported.
(This quirks doesn't mean that driver didn't support the Highseepd mode.)
Note: If driver didn't support the Highspeed Mode, use or add the other
quirks.
After applied this patch, all Exynos SoCs are just running with 25MHz.
Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
---
drivers/mmc/sdhci.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 9fdbed8..1fa4038 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -553,9 +553,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char
*name, int buswidth,
cfg->host_caps |= MMC_MODE_8BIT;
}
- if (quirks & SDHCI_QUIRK_NO_HISPD_BIT)
- cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
-
if (host_caps)
cfg->host_caps |= host_caps;
--
1.9.1
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