On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote: > For some reason the CLKDIV field varies between SoC in how it interprets > the bit values. > > All 83xx and early (e500v1) PQ3 devices support: > clk/2: CLKDIV = 2 > clk/4: CLKDIV = 4 > clk/8: CLKDIV = 8 > > Newer PQ3 (e500v2) and MPC86xx support: > clk/4: CLKDIV = 2 > clk/8: CLKDIV = 4 > clk/16: CLKDIV = 8 > > Ensure that the MPC86xx and MPC85xx still get the same behavior and make > the the defines reflect their logical view (not the value of the field). > > Signed-off-by: Kumar Gala <ga...@kernel.crashing.org>
Acked-by: Peter Tyser <pty...@xes-inc.com> Thanks _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
