The already available ilog2 function does exactly the same in the common
case than the log2 function the current clock-driver reimplement.
So, simply move to that one.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
drivers/clk/rockchip/clk_rk3036.c | 10 +++-------
drivers/clk/rockchip/clk_rk3288.c | 10 +++-------
2 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3036.c
b/drivers/clk/rockchip/clk_rk3036.c
index 6202c9d..8899b0c 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -15,6 +15,7 @@
#include <asm/arch/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3036-cru.h>
+#include <linux/log2.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -48,11 +49,6 @@ enum {
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
-static inline unsigned int log2(unsigned int value)
-{
- return fls(value) - 1;
-}
-
void *rockchip_get_cru(void)
{
struct udevice *dev;
@@ -177,11 +173,11 @@ static void rkclk_init(struct rk3036_cru *cru)
aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
- hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+ hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
assert((1 << hclk_div) * PERI_HCLK_HZ ==
PERI_ACLK_HZ && (pclk_div < 0x4));
- pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+ pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
assert((1 << pclk_div) * PERI_PCLK_HZ ==
PERI_ACLK_HZ && pclk_div < 0x8);
diff --git a/drivers/clk/rockchip/clk_rk3288.c
b/drivers/clk/rockchip/clk_rk3288.c
index e00feb0..c07203d 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -20,6 +20,7 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass-internal.h>
+#include <linux/log2.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -186,11 +187,6 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum
rk_clk_id clk_id,
return 0;
}
-static inline unsigned int log2(unsigned int value)
-{
- return fls(value) - 1;
-}
-
static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
unsigned int hz)
{
@@ -421,11 +417,11 @@ static void rkclk_init(struct rk3288_cru *cru, struct
rk3288_grf *grf)
aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
- hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+ hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
assert((1 << hclk_div) * PERI_HCLK_HZ ==
PERI_ACLK_HZ && (hclk_div < 0x4));
- pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+ pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
assert((1 << pclk_div) * PERI_PCLK_HZ ==
PERI_ACLK_HZ && (pclk_div < 0x4));
--
2.8.1
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