According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "
The current logic is inverted, so fix it to match the reference manual.
Signed-off-by: Fabio Estevam <fabio.este...@nxp.com>
---
arch/arm/cpu/armv7/mx6/clock.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ff932aa..1904c96 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -433,9 +433,9 @@ static u32 get_axi_clk(void)
if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- else
root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
+ else
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
} else
root_freq = get_periph_clk();
--
1.9.1
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