Allow the calibration data from mmdc_do_write_level_calibration
and mmdc_do_dqs_calibration to be returned to the caller for
display.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
arch/arm/cpu/armv7/mx6/ddr.c | 29 +++++++++++++++++++++++------
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 4 ++--
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 1e7ae28..bde6fe3 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -86,7 +86,7 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32
*reg_ctrl)
writel(val_ctrl, reg_ctrl);
}
-int mmdc_do_write_level_calibration(void)
+int mmdc_do_write_level_calibration(struct mx6_mmdc_calibration *calib)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
@@ -195,10 +195,17 @@ int mmdc_do_write_level_calibration(void)
readl(&mmdc1->mpwldectrl1));
/* We must force a readback of these values, to get them to stick */
- readl(&mmdc0->mpwldectrl0);
- readl(&mmdc0->mpwldectrl1);
- readl(&mmdc1->mpwldectrl0);
- readl(&mmdc1->mpwldectrl1);
+ if (calib) {
+ calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
+ calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
+ calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
+ calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
+ } else {
+ readl(&mmdc0->mpwldectrl0);
+ readl(&mmdc0->mpwldectrl1);
+ readl(&mmdc1->mpwldectrl0);
+ readl(&mmdc1->mpwldectrl1);
+ }
/* enable DDR logic power down timer: */
setbits_le32(&mmdc0->mdpdc, 0x00005500);
@@ -212,7 +219,7 @@ int mmdc_do_write_level_calibration(void)
return errors;
}
-int mmdc_do_dqs_calibration(void)
+int mmdc_do_dqs_calibration(struct mx6_mmdc_calibration *calib)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
@@ -548,6 +555,16 @@ int mmdc_do_dqs_calibration(void)
debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
+ if (calib) {
+ calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
+ calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
+ calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
+ calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
+ calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
+ calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
+ calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
+ calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
+ }
return errors;
}
#endif
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 12c30d2..948862c 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -457,8 +457,8 @@ void mx6sl_dram_iocfg(unsigned width,
const struct mx6sl_iomux_grp_regs *);
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-int mmdc_do_write_level_calibration(void);
-int mmdc_do_dqs_calibration(void);
+int mmdc_do_write_level_calibration(struct mx6_mmdc_calibration *calib);
+int mmdc_do_dqs_calibration(struct mx6_mmdc_calibration *calib);
#endif
/* configure mx6 mmdc registers */
--
2.7.4
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