Hi Simon, > -----Original Message----- > From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass > Sent: 2016年6月10日 8:34 > To: Yang, Wenyou <wenyou.y...@atmel.com> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Andreas Bießmann > <andr...@biessmann.org>; Stephen Warren <swar...@wwwdotorg.org> > Subject: Re: [PATCH v2 2/2] clk: at91: Add new clock driver > > +Stephen > > Hi Wenyou, > > On 7 June 2016 at 01:11, Wenyou Yang <wenyou.y...@atmel.com> wrote: > > The patch is referred to at91 clock driver of Linux, to make the clock > > node descriptions in dt are aligned with the Linux. > > > > Signed-off-by: Wenyou Yang <wenyou.y...@atmel.com> > > --- > > > > Changes in v2: > > - Remove the redundant log print. > > > > arch/arm/mach-at91/include/mach/at91_pmc.h | 11 ++- > > drivers/clk/Kconfig | 1 + > > drivers/clk/Makefile | 1 + > > drivers/clk/at91/Kconfig | 14 +++ > > drivers/clk/at91/Makefile | 11 +++ > > drivers/clk/at91/clk-generated.c | 138 > +++++++++++++++++++++++++++++ > > drivers/clk/at91/clk-h32mx.c | 56 ++++++++++++ > > drivers/clk/at91/clk-main.c | 55 ++++++++++++ > > drivers/clk/at91/clk-master.c | 33 +++++++ > > drivers/clk/at91/clk-peripheral.c | 68 ++++++++++++++ > > drivers/clk/at91/clk-plla.c | 55 ++++++++++++ > > drivers/clk/at91/clk-slow.c | 37 ++++++++ > > drivers/clk/at91/clk-system.c | 65 ++++++++++++++ > > drivers/clk/at91/clk-utmi.c | 67 ++++++++++++++ > > drivers/clk/at91/pmc.c | 49 ++++++++++ > > drivers/clk/at91/pmc.h | 17 ++++ > > drivers/clk/at91/sckc.c | 30 +++++++ > > 17 files changed, 705 insertions(+), 3 deletions(-) create mode > > 100644 drivers/clk/at91/Kconfig create mode 100644 > > drivers/clk/at91/Makefile create mode 100644 > > drivers/clk/at91/clk-generated.c create mode 100644 > > drivers/clk/at91/clk-h32mx.c create mode 100644 > > drivers/clk/at91/clk-main.c create mode 100644 > > drivers/clk/at91/clk-master.c create mode 100644 > > drivers/clk/at91/clk-peripheral.c create mode 100644 > > drivers/clk/at91/clk-plla.c create mode 100644 > > drivers/clk/at91/clk-slow.c create mode 100644 > > drivers/clk/at91/clk-system.c create mode 100644 > > drivers/clk/at91/clk-utmi.c create mode 100644 drivers/clk/at91/pmc.c > > create mode 100644 drivers/clk/at91/pmc.h create mode 100644 > > drivers/clk/at91/sckc.c > > > > diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h > > b/arch/arm/mach-at91/include/mach/at91_pmc.h > > index 7684f09..d02f3e1 100644 > > --- a/arch/arm/mach-at91/include/mach/at91_pmc.h > > +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h > > @@ -149,6 +149,9 @@ typedef struct at91_pmc { > > > > #define AT91_PMC_PCR_PID_MASK (0x3f) > > #define AT91_PMC_PCR_GCKCSS (0x7 << 8) > > +#define AT91_PMC_PCR_GCKCSS_MASK 0x07 > > +#define AT91_PMC_PCR_GCKCSS_OFFSET 8 > > +#define AT91_PMC_PCR_GCKCSS_(x) ((x & 0x07) << 8) > > #define AT91_PMC_PCR_GCKCSS_SLOW_CLK (0x0 << 8) > > #define AT91_PMC_PCR_GCKCSS_MAIN_CLK (0x1 << 8) > > #define AT91_PMC_PCR_GCKCSS_PLLA_CLK (0x2 << 8) > > @@ -158,8 +161,9 @@ typedef struct at91_pmc { > > #define AT91_PMC_PCR_CMD_WRITE (0x1 << 12) > > #define AT91_PMC_PCR_DIV (0x3 << 16) > > #define AT91_PMC_PCR_GCKDIV (0xff << 20) > > -#define AT91_PMC_PCR_GCKDIV_(x) ((x & 0xff) << 20) > > -#define AT91_PMC_PCR_GCKDIV_OFFSET 20 > > +#define AT91_PMC_PCR_GCKDIV_MASK 0xff > > +#define AT91_PMC_PCR_GCKDIV_OFFSET 20 > > +#define AT91_PMC_PCR_GCKDIV_(x) ((x & 0xff) << 20) > > #define AT91_PMC_PCR_EN (0x1 << 28) > > #define AT91_PMC_PCR_GCKEN (0x1 << 29) > > > > @@ -243,8 +247,9 @@ typedef struct at91_pmc { > > #define AT91_PMC_PCK1RDY (1 << 9) /* > Programmable Clock 1 */ > > #define AT91_PMC_PCK2RDY (1 << 10) /* > Programmable Clock 2 */ > > #define AT91_PMC_PCK3RDY (1 << 11) /* > Programmable Clock 3 */ > > +#define AT91_PMC_MOSCSELS BIT(16) /* > > Main > Oscillator Selection Status */ > > +#define AT91_PMC_MOSCRCS BIT(17) /* > > 12 MHz > RC Oscillator Status */ > > #define AT91_PMC_GCKRDY (1 << 24) > > - > > #define AT91_PMC_PROTKEY 0x504d4301 /* > > Activation > Code */ > > > > /* PLL Charge Pump Current Register (PMC_PLLICPR) */ diff --git > > a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a98b74b..1fd1074 > > 100644 > > --- a/drivers/clk/Kconfig > > +++ b/drivers/clk/Kconfig > > @@ -21,5 +21,6 @@ config SPL_CLK > > used as U-Boot proper. > > > > source "drivers/clk/uniphier/Kconfig" > > +source "drivers/clk/at91/Kconfig" > > > > endmenu > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index > > c51db15..2bb0f35 100644 > > --- a/drivers/clk/Makefile > > +++ b/drivers/clk/Makefile > > @@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o > > obj-$(CONFIG_SANDBOX) += clk_sandbox.o > > obj-$(CONFIG_MACH_PIC32) += clk_pic32.o > > obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ > > +obj-$(CONFIG_CLK_AT91) += at91/ > > diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig new > > file mode 100644 index 0000000..f9cb937 > > --- /dev/null > > +++ b/drivers/clk/at91/Kconfig > > @@ -0,0 +1,14 @@ > > +config CLK_AT91 > > + bool "AT91 clock drivers" > > + depends on CLK > > + help > > + This option is used to enable the AT91 clock driver. > > + > > +config HAVE_AT91_UTMI > > + bool > > + > > +config HAVE_AT91_H32MX > > + bool > > + > > +config HAVE_AT91_GENERATED_CLK > > + bool > > Please can you add help?
Accepted. > > Also we are changing the clock interface - please see this patch: > > http://patchwork.ozlabs.org/patch/625342/ > > I'm hoping to bring it in next week. > > > diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile new > > file mode 100644 index 0000000..eb1326b > > --- /dev/null > > +++ b/drivers/clk/at91/Makefile > > @@ -0,0 +1,11 @@ > > +# > > +# Makefile for at91 specific clk > > +# > > + > > +obj-y += pmc.o sckc.o > > +obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o obj-y += > > +clk-system.o clk-peripheral.o > > + > > +obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o > > +obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o > > +obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o > > diff --git a/drivers/clk/at91/clk-generated.c > > b/drivers/clk/at91/clk-generated.c > > new file mode 100644 > > index 0000000..08e7a2f > > --- /dev/null > > +++ b/drivers/clk/at91/clk-generated.c > > @@ -0,0 +1,138 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <linux/io.h> > > +#include <mach/at91_pmc.h> > > +#include "pmc.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +#define GENERATED_SOURCE_MAX 6 > > +#define GENERATED_MAX_DIV 255 > > + > > +static ulong generated_clk_get_periph_rate(struct udevice *dev, int > > +periph) { > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + struct at91_pmc *pmc = plat->reg_base; > > + struct udevice *parent; > > + u32 tmp, gckdiv; > > + u8 parent_id; > > + int ret; > > + > > + writel(periph & AT91_PMC_PCR_PID_MASK, &pmc->pcr); > > + tmp = readl(&pmc->pcr); > > + parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) & > > + AT91_PMC_PCR_GCKCSS_MASK; > > + gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & > > + AT91_PMC_PCR_GCKDIV_MASK; > > + > > + ret = clk_get_by_index(dev, parent_id, &parent); > > + if (ret) > > + return 0; > > + > > + return clk_get_rate(parent) / (gckdiv + 1); } > > + > > +static ulong generated_clk_set_periph_rate(struct udevice *dev, > > + int periph, > > + ulong rate) { > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + struct at91_pmc *pmc = plat->reg_base; > > + struct udevice *parent, *best_parent = NULL; > > + ulong tmp_rate, best_rate = rate, parent_rate; > > + int tmp_diff, best_diff = -1; > > + u8 num_parents, i; > > + u32 cells[GENERATED_SOURCE_MAX]; > > + u32 div, best_div = 0; > > + u8 best_parent_id = 0; > > + u32 tmp; > > + int ret; > > + > > + num_parents = fdtdec_get_int_array_count(gd->fdt_blob, > > dev->of_offset, > > + "clocks", cells, > > + > > + GENERATED_SOURCE_MAX); > > Are you able to store this value in your priv data in your > of_to_platdata() method? We should not be looking at the device tree outside > that > method. Okay, move it to ofdata_to_platdata(). > > > + > > + for (i = 0; i < num_parents; i++) { > > + ret = clk_get_by_index(dev, i, &parent); > > + if (ret) > > + return ret; > > + > > + parent_rate = clk_get_rate(parent); > > + if (!parent_rate) > > + return -ENODEV; > > + > > + for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { > > + tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); > > + if (rate < tmp_rate) > > + continue; > > + tmp_diff = rate - tmp_rate; > > + > > + if (best_diff < 0 || best_diff > tmp_diff) { > > + best_rate = tmp_rate; > > + best_diff = tmp_diff; > > + > > + best_div = div - 1; > > + best_parent = parent; > > + best_parent_id = i; > > + } > > + > > + if (!best_diff || tmp_rate < rate) > > + break; > > + } > > + > > + if (!best_diff) > > + break; > > + } > > + > > + dev_dbg(dev, "GCK: best parent: %s, best_rate = %ld, best_div = > > %d\n", > > + best_parent->name, best_rate, best_div); > > + > > + ret = clk_enable(best_parent, 0); > > + if (ret) > > + return -ENODEV; > > + > > + writel(periph & AT91_PMC_PCR_PID_MASK, &pmc->pcr); > > + tmp = readl(&pmc->pcr); > > + tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS); > > + tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) | > > + AT91_PMC_PCR_CMD_WRITE | > > + AT91_PMC_PCR_GCKDIV_(best_div) | > > + AT91_PMC_PCR_GCKEN; > > + writel(tmp, &pmc->pcr); > > + > > + while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY)) > > + ; > > + > > + return 0; > > +} > > + > > +static struct clk_ops generated_clk_ops = { > > + .get_periph_rate = generated_clk_get_periph_rate, > > + .set_periph_rate = generated_clk_set_periph_rate, }; > > + > > +static int generated_clk_probe(struct udevice *dev) { > > + return at91_pmc_core_probe(dev); } > > + > > +static const struct udevice_id generated_clk_match[] = { > > + { .compatible = "atmel,sama5d2-clk-generated" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(generated_clk) = { > > + .name = "generated-clk", > > + .id = UCLASS_CLK, > > + .of_match = generated_clk_match, > > + .probe = generated_clk_probe, > > + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), > > + .ops = &generated_clk_ops, > > +}; > > diff --git a/drivers/clk/at91/clk-h32mx.c > > b/drivers/clk/at91/clk-h32mx.c new file mode 100644 index > > 0000000..035562a > > --- /dev/null > > +++ b/drivers/clk/at91/clk-h32mx.c > > @@ -0,0 +1,56 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <dm/util.h> > > +#include <linux/io.h> > > +#include <mach/at91_pmc.h> > > +#include "pmc.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +#define H32MX_MAX_FREQ 90000000 > > + > > +static ulong sama5d4_h32mx_clk_get_rate(struct udevice *dev) { > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + struct at91_pmc *pmc = plat->reg_base; > > + ulong rate = gd->arch.mck_rate_hz; > > + > > + if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV) > > + rate /= 2; > > + > > + if (rate > H32MX_MAX_FREQ) > > + dm_warn("H32MX clock is too fast\n"); > > + > > + return rate; > > +} > > + > > +static struct clk_ops sama5d4_h32mx_clk_ops = { > > + .get_rate = sama5d4_h32mx_clk_get_rate, }; > > + > > +static int sama5d4_h32mx_clk_probe(struct udevice *dev) { > > + return at91_pmc_core_probe(dev); } > > + > > +static const struct udevice_id sama5d4_h32mx_clk_match[] = { > > + { .compatible = "atmel,sama5d4-clk-h32mx" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(sama5d4_h32mx_clk) = { > > + .name = "sama5d4-h32mx-clk", > > + .id = UCLASS_CLK, > > + .of_match = sama5d4_h32mx_clk_match, > > + .probe = sama5d4_h32mx_clk_probe, > > + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), > > + .ops = &sama5d4_h32mx_clk_ops, }; > > diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c > > new file mode 100644 index 0000000..10ab951 > > --- /dev/null > > +++ b/drivers/clk/at91/clk-main.c > > @@ -0,0 +1,55 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <linux/io.h> > > +#include <mach/at91_pmc.h> > > +#include "pmc.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static int main_osc_clk_enable(struct udevice *dev, int periph) { > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + struct at91_pmc *pmc = plat->reg_base; > > + > > + if (readl(&pmc->sr) & AT91_PMC_MOSCSELS) > > + return 0; > > + > > + return -ENODEV; > > This error indicates that there is no device. But it looks like there is. > What are you > trying to represent here? It is supposed that the main oscillator clock should be enabled, if it is not enabled, it is an error, return -EINVAL? > > > +} > > + > > +static ulong main_osc_clk_get_rate(struct udevice *dev) { > > + return gd->arch.main_clk_rate_hz; } > > + > > +static struct clk_ops main_osc_clk_ops = { > > + .enable = main_osc_clk_enable, > > + .get_rate = main_osc_clk_get_rate, }; > > + > > +static int main_osc_clk_probe(struct udevice *dev) { > > + return at91_pmc_core_probe(dev); } > > + > > +static const struct udevice_id main_osc_clk_match[] = { > > + { .compatible = "atmel,at91sam9x5-clk-main" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = { > > + .name = "at91sam9x5-main-osc-clk", > > + .id = UCLASS_CLK, > > + .of_match = main_osc_clk_match, > > + .probe = main_osc_clk_probe, > > + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), > > + .ops = &main_osc_clk_ops, > > +}; > > diff --git a/drivers/clk/at91/clk-master.c > > b/drivers/clk/at91/clk-master.c new file mode 100644 index > > 0000000..6d844d0 > > --- /dev/null > > +++ b/drivers/clk/at91/clk-master.c > > @@ -0,0 +1,33 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static ulong at91_master_clk_get_rate(struct udevice *dev) { > > + return gd->arch.mck_rate_hz; > > +} > > + > > +static struct clk_ops at91_master_clk_ops = { > > + .get_rate = at91_master_clk_get_rate, }; > > + > > +static const struct udevice_id at91_master_clk_match[] = { > > + { .compatible = "atmel,at91sam9x5-clk-master" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(at91_master_clk) = { > > + .name = "at91-master-clk", > > + .id = UCLASS_CLK, > > + .of_match = at91_master_clk_match, > > + .ops = &at91_master_clk_ops, > > +}; > > diff --git a/drivers/clk/at91/clk-peripheral.c > > b/drivers/clk/at91/clk-peripheral.c > > new file mode 100644 > > index 0000000..4faeca5 > > --- /dev/null > > +++ b/drivers/clk/at91/clk-peripheral.c > > @@ -0,0 +1,68 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <linux/io.h> > > +#include <mach/at91_pmc.h> > > +#include "pmc.h" > > + > > +#define PERIPHERAL_MAX 64 > > + > > +#define PERIPHERAL_AT91RM9200 0 > > +#define PERIPHERAL_AT91SAM9X5 1 > > + > > +#define PERIPHERAL_ID_MIN 2 > > +#define PERIPHERAL_ID_MAX 31 > > +#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX)) > > + > > +#define PERIPHERAL_RSHIFT_MASK 0x3 > > +#define PERIPHERAL_RSHIFT(val) (((val) >> 16) & > > +PERIPHERAL_RSHIFT_MASK) > > + > > +#define PERIPHERAL_MAX_SHIFT 3 > > + > > +static int sam9x5_periph_clk_enable(struct udevice *dev, int periph) > > +{ > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + struct at91_pmc *pmc = plat->reg_base; > > + u32 tmp; > > + > > + if (periph < PERIPHERAL_ID_MIN) > > + return -1; > > + > > + writel(periph & AT91_PMC_PCR_PID_MASK, &pmc->pcr); > > + tmp = readl(&pmc->pcr); > > + writel(tmp | > > + AT91_PMC_PCR_CMD_WRITE | > > + AT91_PMC_PCR_EN, &pmc->pcr); > > Or use setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE | > AT91_PMC_PCR_EN) Accepted. > > > + > > + return 0; > > +} > > + > > +static struct clk_ops sam9x5_periph_clk_ops = { > > + .enable = sam9x5_periph_clk_enable, }; > > + > > +static int sam9x5_periph_clk_probe(struct udevice *dev) { > > + return at91_pmc_core_probe(dev); } > > + > > +static const struct udevice_id sam9x5_periph_clk_match[] = { > > + { .compatible = "atmel,at91sam9x5-clk-peripheral" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(sam9x5_periph_clk) = { > > + .name = "sam9x5-periph-clk", > > + .id = UCLASS_CLK, > > + .of_match = sam9x5_periph_clk_match, > > + .probe = sam9x5_periph_clk_probe, > > + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), > > + .ops = &sam9x5_periph_clk_ops, }; > > diff --git a/drivers/clk/at91/clk-plla.c b/drivers/clk/at91/clk-plla.c > > new file mode 100644 index 0000000..3a2168e > > --- /dev/null > > +++ b/drivers/clk/at91/clk-plla.c > > @@ -0,0 +1,55 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <linux/io.h> > > +#include <mach/at91_pmc.h> > > +#include "pmc.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static int plla_clk_enable(struct udevice *dev, int periph) { > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + struct at91_pmc *pmc = plat->reg_base; > > + > > + if (readl(&pmc->sr) & AT91_PMC_LOCKA) > > + return 0; > > + > > + return -ENODEV; > > Same error question here. > > > +} > > + > > +static ulong plla_clk_get_rate(struct udevice *dev) { > > + return gd->arch.plla_rate_hz; > > +} > > + > > +static struct clk_ops plla_clk_ops = { > > + .enable = plla_clk_enable, > > + .get_rate = plla_clk_get_rate, }; > > + > > +static int plla_clk_probe(struct udevice *dev) { > > + return at91_pmc_core_probe(dev); } > > + > > +static const struct udevice_id plla_clk_match[] = { > > + { .compatible = "atmel,sama5d3-clk-pll" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(at91_plla_clk) = { > > + .name = "at91-plla-clk", > > + .id = UCLASS_CLK, > > + .of_match = plla_clk_match, > > + .probe = plla_clk_probe, > > + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), > > + .ops = &plla_clk_ops, > > +}; > > diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c > > new file mode 100644 index 0000000..f73a553 > > --- /dev/null > > +++ b/drivers/clk/at91/clk-slow.c > > @@ -0,0 +1,37 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > + > > +static int at91_slow_clk_enable(struct udevice *dev, int periph) { > > + return 0; > > +} > > + > > +static ulong at91_slow_clk_get_rate(struct udevice *dev) { > > + return CONFIG_SYS_AT91_SLOW_CLOCK; } > > + > > +static struct clk_ops at91_slow_clk_ops = { > > + .enable = at91_slow_clk_enable, > > + .get_rate = at91_slow_clk_get_rate, }; > > + > > +static const struct udevice_id at91_slow_clk_match[] = { > > + { .compatible = "atmel,at91sam9x5-clk-slow" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(at91_slow_clk) = { > > + .name = "at91-slow-clk", > > + .id = UCLASS_CLK, > > + .of_match = at91_slow_clk_match, > > + .ops = &at91_slow_clk_ops, > > +}; > > diff --git a/drivers/clk/at91/clk-system.c > > b/drivers/clk/at91/clk-system.c new file mode 100644 index > > 0000000..5e50af6 > > --- /dev/null > > +++ b/drivers/clk/at91/clk-system.c > > @@ -0,0 +1,65 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <linux/io.h> > > +#include <mach/at91_pmc.h> > > +#include "pmc.h" > > + > > +#define SYSTEM_MAX_ID 31 > > + > > +static inline int is_pck(int id) > > +{ > > + return (id >= 8) && (id <= 15); } > > + > > +static int at91_system_clk_enable(struct udevice *dev, int id) { > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + struct at91_pmc *pmc = plat->reg_base; > > + u32 mask; > > + > > + if (id > SYSTEM_MAX_ID) > > + return -EINVAL; > > + > > + mask = BIT(id); > > + > > + writel(mask, &pmc->scer); > > + > > + if (!is_pck(id)) > > + return 0; > > Please can you add a comment to explain the above two lines? Accepted. > > > + > > + while (!(readl(&pmc->sr) & mask)) > > + ; > > + > > + return 0; > > +} > > + > > +static struct clk_ops at91_system_clk_ops = { > > + .enable = at91_system_clk_enable, }; > > + > > +static int at91_system_clk_probe(struct udevice *dev) { > > + return at91_pmc_core_probe(dev); } > > + > > +static const struct udevice_id at91_system_clk_match[] = { > > + { .compatible = "atmel,at91rm9200-clk-system" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(at91_system_clk) = { > > + .name = "at91-system-clk", > > + .id = UCLASS_CLK, > > + .of_match = at91_system_clk_match, > > + .probe = at91_system_clk_probe, > > + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), > > + .ops = &at91_system_clk_ops, > > +}; > > diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c > > new file mode 100644 index 0000000..835c611 > > --- /dev/null > > +++ b/drivers/clk/at91/clk-utmi.c > > @@ -0,0 +1,67 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <linux/io.h> > > +#include <mach/at91_pmc.h> > > +#include "pmc.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +#define UTMI_FIXED_MUL 40 > > + > > +static int utmi_clk_enable(struct udevice *dev, int periph) { > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + struct at91_pmc *pmc = plat->reg_base; > > + u32 tmp; > > + > > + if (readl(&pmc->sr) & AT91_PMC_LOCKU) > > + return 0; > > + > > + tmp = readl(&pmc->uckr); > > + tmp |= AT91_PMC_UPLLEN | > > + AT91_PMC_UPLLCOUNT | > > + AT91_PMC_BIASEN; > > + writel(tmp, &pmc->uckr); > > + > > + while (!(readl(&pmc->sr) & AT91_PMC_LOCKU)) > > + ; > > + > > + return 0; > > +} > > + > > +static ulong utmi_clk_get_rate(struct udevice *dev) { > > + return gd->arch.main_clk_rate_hz * UTMI_FIXED_MUL; } > > + > > +static struct clk_ops utmi_clk_ops = { > > + .enable = utmi_clk_enable, > > + .get_rate = utmi_clk_get_rate, }; > > + > > +static int utmi_clk_probe(struct udevice *dev) { > > + return at91_pmc_core_probe(dev); } > > + > > +static const struct udevice_id utmi_clk_match[] = { > > + { .compatible = "atmel,at91sam9x5-clk-utmi" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(at91sam9x5_utmi_clk) = { > > + .name = "at91sam9x5-utmi-clk", > > + .id = UCLASS_CLK, > > + .of_match = utmi_clk_match, > > + .probe = utmi_clk_probe, > > + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), > > + .ops = &utmi_clk_ops, > > +}; > > diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c new file > > mode 100644 index 0000000..de802e8 > > --- /dev/null > > +++ b/drivers/clk/at91/pmc.c > > @@ -0,0 +1,49 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <dm/root.h> > > +#include "pmc.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static int at91_pmc_core_bind(struct udevice *dev) { > > + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, > > +false); } > > + > > +static const struct udevice_id at91_pmc_core_match[] = { > > + { .compatible = "atmel,sama5d2-pmc" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(at91_pmc_core) = { > > + .name = "at91_pmc_core", > > + .id = UCLASS_CLK, > > + .of_match = at91_pmc_core_match, > > + .bind = at91_pmc_core_bind, > > +}; > > + > > +int at91_pmc_core_probe(struct udevice *dev) { > > + struct pmc_platdata *plat = dev_get_platdata(dev); > > + fdt_addr_t addr; > > + > > + dev = dev_get_parent(dev); > > + if (!dev) > > + return -EINVAL; > > There will always be a parent, so this test is redundant. Accepted. > > > + > > + addr = dev_get_addr(dev); > > + if (addr == FDT_ADDR_T_NONE) > > + return -EINVAL; > > You can use dev_get_addr_ptr() here. Accepted. > > > + > > + plat->reg_base = (struct at91_pmc *)addr; > > + > > + return 0; > > +} > > diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h new file > > mode 100644 index 0000000..201dad8 > > --- /dev/null > > +++ b/drivers/clk/at91/pmc.h > > @@ -0,0 +1,17 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#ifndef __AT91_PMC_H__ > > +#define __AT91_PMC_H__ > > + > > +struct pmc_platdata { > > + struct at91_pmc *reg_base; > > +}; > > + > > +int at91_pmc_core_probe(struct udevice *dev); > > + > > +#endif > > diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c new > > file mode 100644 index 0000000..69ec636 > > --- /dev/null > > +++ b/drivers/clk/at91/sckc.c > > @@ -0,0 +1,30 @@ > > +/* > > + * Copyright (C) 2016 Atmel Corporation > > + * Wenyou.Yang <wenyou.y...@atmel.com> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <clk.h> > > +#include <dm/device.h> > > +#include <dm/root.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static int at91_sckc_clk_bind(struct udevice *dev) { > > + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, > > +false); } > > + > > +static const struct udevice_id at91_sckc_clk_match[] = { > > + { .compatible = "atmel,at91sam9x5-sckc" }, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(at91_sckc_clk) = { > > + .name = "at91_sckc_clk", > > + .id = UCLASS_CLK, > > + .of_match = at91_sckc_clk_match, > > + .bind = at91_sckc_clk_bind, > > +}; > > -- > > 2.7.4 > > > > Regards, > Simon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
