2016-06-08 18:02 GMT+09:00 Masahiro Yamada <yamada.masah...@socionext.com>: > I noticed secondary CPUs sometimes fail to wake up, and the root > cause is that the sev instruction wakes up slave CPUs before the > preceding the register write is observed by them. > > The read-back of the accessed register does not guarantee the order. > In order to ensure the order between the register write and the sev > instruction, a dsb instruction should be executed prior to the sev. > > Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
