From: Yuan Yao <yao.y...@nxp.com>
When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux.
So enable I2C QIXIS access and I2C early init to read the
sysclk and ddrclk.
Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v5:
Use I2C to read the clocks instead of the hard-coded clocks.
---
board/freescale/ls2080aqds/ls2080aqds.c | 3 +++
include/configs/ls2080aqds.h | 10 ++++++++++
2 files changed, 13 insertions(+)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index d7acb48..19bb4c6 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -219,6 +219,9 @@ int board_init(void)
int board_early_init_f(void)
{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
#ifdef CONFIG_FSL_QSPI
/* input clk: 1/2 platform clk, output: input/20 */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..ccc987c 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,6 +17,16 @@ unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
+#endif
+
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
--
2.1.0.27.g96db324
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