On 05/30/2016 08:18 PM, Shengzhou Liu wrote: > >> -----Original Message----- >> From: York Sun [mailto:york....@nxp.com] >> Sent: Tuesday, May 17, 2016 12:55 AM >> To: Shengzhou Liu <shengzhou....@nxp.com>; u-boot@lists.denx.de >> Subject: Re: [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl > >> >> Shengzhou, >> >> Your understanding is correct. However, we have done analysis that the >> additional bit is not used for finer adjustment. So unless you have a case >> requiring values in the middle, I suggest to keep current code. >> >> York > > York > > On LS1046RDB, the clk_adj is 9, an odd instead of even data, so we have to > update it, and there will be more new boards in future with possibly odd > clk_adj. >
Shengzhou, If you have to use an odd number for clk_adj, we can go ahead to merge these patches. In my experience, clk_adj is very forgivable. If you have only one value works, there is probably something wrong. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
