Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.
Signed-off-by: Wills Wang <wills.w...@live.com>
---
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 +
arch/mips/mach-ath79/reset.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index dabcad0..7b48524 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -331,6 +331,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLK_CTRL_REG 0x08
#define AR933X_PLL_DITHER_FRAC_REG 0x10
+#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index a5ee141..073a179 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -89,7 +89,7 @@ static int eth_init_ar933x(void)
mdelay(10);
/* Get Atheros S26 PHY out of reset. */
- clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+ clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
0x1f, 0x10);
mdelay(10);
--
1.9.1
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
