On 04/14/2016 08:57 PM, Yunhui Cui wrote:
> From: Yunhui Cui <yunhui....@nxp.com>
>
> The SP805-WDT module on LS2080A and LS2085A, requires configuration
> of PMU's PCTBENR register to enable watchdog counter decrement and
> reset signal generation. In order not to affect the sp805wdt driver
> frame, we enable the watchdog clk in advance.
>
> Signed-off-by: Yunhui Cui <yunhui....@nxp.com>
> ---
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 15 +++++++++++++++
> arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++++
> arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
> board/freescale/ls2080aqds/ls2080aqds.c | 2 ++
> board/freescale/ls2080ardb/ls2080ardb.c | 2 ++
> 5 files changed, 24 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 0cb0100..c36976d 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -42,6 +42,21 @@ bool soc_has_aiop(void)
> return false;
> }
>
> +#if defined(CONFIG_LS2080A)
> +/*
> + * In certain Layerscape SoCs, the clock for each core's watchdog
> + * has an enable bit in the PMU Physical Core Time Base Enable Register
> + * (PCTBENR), which allows the watchdog to operate.
> + */
> +void enable_watchdog_clk(void)
> +{
> + u32 pmu_val;
> +
> + pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
> + *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff;
> +}
> +#endif
> +
> #ifdef CONFIG_LS2080A
> /*
> * This erratum requires setting a value to eddrtqcr1 to
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index 10d17b2..62e4f95 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -143,6 +143,10 @@
> #define CONFIG_ARM_ERRATA_829520
> #define CONFIG_ARM_ERRATA_833471
>
> +/* PMU-Physical Core Time Base Enable Register */
> +#define FSL_PMU_REG_BASE 0x1E30000
> +#define FSL_PMU_PCTBENR_OFFSET 0x8A0
> +
> #elif defined(CONFIG_LS1043A)
> #define CONFIG_MAX_CPUS 4
> #define CONFIG_SYS_CACHELINE_SIZE 64
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> index 831d817..bd4a8f1 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> @@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);
> #endif
>
> void cpu_name(char *name);
> +void enable_watchdog_clk(void);
> #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> void erratum_a009635(void);
> #endif
> diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
> b/board/freescale/ls2080aqds/ls2080aqds.c
> index b3bd40a..c109349 100644
> --- a/board/freescale/ls2080aqds/ls2080aqds.c
> +++ b/board/freescale/ls2080aqds/ls2080aqds.c
> @@ -213,6 +213,8 @@ int board_init(void)
> select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
> rtc_enable_32khz_output();
>
> + enable_watchdog_clk();
> +
> return 0;
> }
>
> diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
> b/board/freescale/ls2080ardb/ls2080ardb.c
> index fb39af6..7872f1f 100644
> --- a/board/freescale/ls2080ardb/ls2080ardb.c
> +++ b/board/freescale/ls2080ardb/ls2080ardb.c
> @@ -181,6 +181,8 @@ int board_init(void)
> /* invert AQR405 IRQ pins polarity */
> out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
>
> + enable_watchdog_clk();
> +
> return 0;
> }
>
>
Yunhui,
I think you can move your code into timer_init() in cpu.c and follow the example
of cltbenr.
York
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