#include "microcode/m12306a9_0000001b.dtsi"
};
};
diff --git a/arch/x86/dts/chromebook_samus.dts
b/arch/x86/dts/chromebook_samus.dts
index 5dd3e57..103e26f 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -65,7 +65,7 @@
intel,duplicate-por;
};
- pch_pinctrl {
+ pch_pinctrl@0 {
compatible = "intel,x86-broadwell-pinctrl";
u-boot,dm-pre-reloc;
reg = <0 0>;
@@ -131,7 +131,7 @@
pirq-apic = <PIRQ_APIC_ROUTE>;
};
- soc_gpio@0 {
+ soc_gpio {
config =
<0 &gpio_unused 0>, /* unused */
<1 &gpio_unused 0>, /* unused */
@@ -231,7 +231,7 @@
};
};
- pci {
+ pci@0 {
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
@@ -249,7 +249,7 @@
spd {
#address-cells = <1>;
#size-cells = <0>;
- samsung_4 {
+ samsung_4@6 {
reg = <6>;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
@@ -284,7 +284,7 @@
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
- hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
+ hynix-h9ccnnnbltmlar-ntm-lpddr3-32@8 {
/*
* banks 8, ranks 2, rows 14,
* columns 10, density 4096 mb, x32
@@ -323,7 +323,7 @@
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
- samsung_8 {
+ samsung_8@10 {
reg = <10>;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
@@ -358,7 +358,7 @@
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
- hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
+ hynix-h9ccnnnbltmlar-ntm-lpddr3-16@12 {
/*
* banks 8, ranks 2, rows 14,
* columns 11, density 4096 mb, x16
@@ -397,7 +397,7 @@
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
- hynix-h9ccnnncltmlar-lpddr3 {
+ hynix-h9ccnnncltmlar-lpddr3@13 {
/*
* banks 8, ranks 2, rows 15,
* columns 11, density 8192 mb, x16
@@ -436,7 +436,7 @@
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
- elpida-edfb232a1ma {
+ elpida-edfb232a1ma@15 {
/*
* banks 8, ranks 2, rows 15,
* columns 11, density 8192 mb, x16
@@ -539,14 +539,14 @@
compatible = "winbond,w25q64",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
+ rw-mrc-cache@3e0000 {
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
};
};
};
- gpio_a: gpioa {
+ gpio_a: gpioa@0 {
compatible = "intel,broadwell-gpio";
u-boot,dm-pre-reloc;
#gpio-cells = <2>;
@@ -555,7 +555,7 @@
bank-name = "A";
};
- gpio_b: gpiob {
+ gpio_b: gpiob@1 {
compatible = "intel,broadwell-gpio";
u-boot,dm-pre-reloc;
#gpio-cells = <2>;
@@ -564,7 +564,7 @@
bank-name = "B";
};
- gpio_c: gpioc {
+ gpio_c: gpioc@2 {
compatible = "intel,broadwell-gpio";
u-boot,dm-pre-reloc;
#gpio-cells = <2>;
@@ -614,13 +614,13 @@
};
};
- tpm {
+ tpm@fed40000 {
reg = <0xfed40000 0x5000>;
compatible = "infineon,slb9635lpc";
};
microcode {
- update@0 {
+ update_1 {
#include "microcode/mc0306d4_00000018.dtsi"
};
};
diff --git a/arch/x86/dts/chromebox_panther.dts
b/arch/x86/dts/chromebox_panther.dts
index 480b366..4f88778 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -22,7 +22,7 @@
stdout-path = "/serial";
};
- pci {
+ pci@0 {
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
@@ -48,28 +48,28 @@
compatible = "winbond,w25q64",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
+ rw-mrc-cache@3e0000 {
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
};
};
};
- gpioa {
+ gpioa@0 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x10>;
bank-name = "A";
};
- gpiob {
+ gpiob@30 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x30 0x10>;
bank-name = "B";
};
- gpioc {
+ gpioc@40 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x10>;
@@ -78,7 +78,7 @@
};
};
- tpm {
+ tpm@fed40000 {
reg = <0xfed40000 0x5000>;
compatible = "infineon,slb9635lpc";
};
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 478dece..e0da067 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -69,7 +69,7 @@
};
};
- pci {
+ pci@0 {
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
@@ -159,49 +159,49 @@
compatible = "stmicro,n25q064a",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
+ rw-mrc-cache@6f0000 {
label = "rw-mrc-cache";
reg = <0x006f0000 0x00010000>;
};
};
};
- gpioa {
+ gpioa@0 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
- gpiob {
+ gpiob@20 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
};
- gpioc {
+ gpioc@40 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x20>;
bank-name = "C";
};
- gpiod {
+ gpiod@60 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x60 0x20>;
bank-name = "D";
};
- gpioe {
+ gpioe@80 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x80 0x20>;
bank-name = "E";
};
- gpiof {
+ gpiof@a0 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0xA0 0x20>;
@@ -268,10 +268,10 @@
};
microcode {
- update@0 {
+ update_0 {
#include "microcode/m0130673322.dtsi"
};
- update@1 {
+ update_1 {
#include "microcode/m0130679901.dtsi"
};
};
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index d415566..b2637b8 100644
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -29,19 +29,19 @@
};
microcode {
- update@0 {
+ update_0 {
#include "microcode/m12306a2_00000008.dtsi"
};
- update@1 {
+ update_1 {
#include "microcode/m12306a4_00000007.dtsi"
};
- update@2 {
+ update_2 {
#include "microcode/m12306a5_00000007.dtsi"
};
- update@3 {
+ update_3 {
#include "microcode/m12306a8_00000010.dtsi"
};
- update@4 {
+ update_4 {
#include "microcode/m12306a9_0000001b.dtsi"
};
};
@@ -51,7 +51,7 @@
fsp,enable-ht;
};
- pci {
+ pci@0 {
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-x86";
@@ -78,21 +78,21 @@
};
};
- gpioa {
+ gpioa@10 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x10>;
bank-name = "A";
};
- gpiob {
+ gpiob@30 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x30 0x10>;
bank-name = "B";
};
- gpioc {
+ gpioc@40 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x10>;
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 337513b..4cd9b4d 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -59,12 +59,12 @@
};
microcode {
- update@0 {
+ update_0 {
#include "microcode/m0220661105_cv.dtsi"
};
};
- pci {
+ pci@0 {
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-x86";
@@ -227,14 +227,14 @@
};
};
- gpioa {
+ gpioa@0 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
- gpiob {
+ gpiob@20 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 21c3641..f2cd456 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -56,7 +56,7 @@
dram-faw = <0x00009c40>;
};
- pci {
+ pci@0 {
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-x86";
@@ -128,21 +128,21 @@
compatible = "winbond,w25q64",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
+ rw-mrc-cache@10000 {
label = "rw-mrc-cache";
reg = <0x00010000 0x00010000>;
};
};
};
- gpioa {
+ gpioa@0 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
- gpiob {
+ gpiob@20 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 60bd05a..37ab8ae 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -31,7 +31,7 @@
compatible = "intel,x86-pinctrl";
/* GPIO E0 */
- soc_gpio_s5_0@0 {
+ soc_gpio_s5_0 {
gpio-offset = <0x80 0>;
pad-offset = <0x1d0>;
mode-gpio;
@@ -40,7 +40,7 @@
};
/* GPIO E1 */
- soc_gpio_s5_1@0 {
+ soc_gpio_s5_1 {
gpio-offset = <0x80 1>;
pad-offset = <0x210>;
mode-gpio;
@@ -49,7 +49,7 @@
};
/* GPIO E2 */
- soc_gpio_s5_2@0 {
+ soc_gpio_s5_2 {
gpio-offset = <0x80 2>;
pad-offset = <0x1e0>;
mode-gpio;
@@ -57,7 +57,7 @@
direction = <PIN_OUTPUT>;
};
- pin_usb_host_en0@0 {
+ pin_usb_host_en0 {
gpio-offset = <0x80 8>;
pad-offset = <0x260>;
mode-gpio;
@@ -65,7 +65,7 @@
direction = <PIN_OUTPUT>;
};
- pin_usb_host_en1@0 {
+ pin_usb_host_en1 {
gpio-offset = <0x80 9>;
pad-offset = <0x250>;
mode-gpio;
@@ -98,7 +98,7 @@
};
- pci {
+ pci@0 {
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
@@ -188,49 +188,49 @@
compatible = "stmicro,n25q064a",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
+ rw-mrc-cache@6f0000 {
label = "rw-mrc-cache";
reg = <0x006f0000 0x00010000>;
};
};
};
- gpioa {
+ gpioa@0 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
- gpiob {
+ gpiob@20 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
};
- gpioc {
+ gpioc@40 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x20>;
bank-name = "C";
};
- gpiod {
+ gpiod@60 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x60 0x20>;
bank-name = "D";
};
- gpioe {
+ gpioe@80 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x80 0x20>;
bank-name = "E";
};
- gpiof {
+ gpiof@a0 {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0xA0 0x20>;
@@ -296,10 +296,10 @@
};
microcode {
- update@0 {
+ update_0 {
#include "microcode/m0130673322.dtsi"
};
- update@1 {
+ update_1 {
#include "microcode/m0130679901.dtsi"
};
};
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 9c3f2a0..3d81e9d 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -42,7 +42,7 @@
clock-frequency = <1000000000>;
};
- pci {
+ pci@0 {
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 5d601b3..931c258 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -53,7 +53,7 @@
clock-frequency = <1000000000>;
};
- pci {
+ pci@0 {
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi
index 1797e04..9b09d7e 100644
--- a/arch/x86/dts/rtc.dtsi
+++ b/arch/x86/dts/rtc.dtsi
@@ -1,5 +1,5 @@
/ {
- rtc {
+ rtc@70 {
compatible = "motorola,mc146818";
u-boot,dm-pre-reloc;
reg = <0x70 2>;
diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 54c3faf..02be132 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -1,5 +1,5 @@
/ {
- serial: serial {
+ serial: serial@3f8 {
compatible = "ns16550";
reg = <0x3f8 8>;
reg-shift = <0>;
diff --git a/arch/x86/dts/skeleton.dtsi b/arch/x86/dts/skeleton.dtsi
index b41d241..a20da0a 100644
--- a/arch/x86/dts/skeleton.dtsi
+++ b/arch/x86/dts/skeleton.dtsi
@@ -9,5 +9,5 @@
#size-cells = <1>;
chosen { };
aliases { };
- memory { device_type = "memory"; reg = <0 0>; };
+ memory@0 { device_type = "memory"; reg = <0 0>; };
};
diff --git a/doc/device-tree-bindings/pmic/sandbox.txt
b/doc/device-tree-bindings/pmic/sandbox.txt
index d84c977..c1bef4c 100644
--- a/doc/device-tree-bindings/pmic/sandbox.txt
+++ b/doc/device-tree-bindings/pmic/sandbox.txt
@@ -24,7 +24,7 @@ Optional subnodes:
Example:
-sandbox_pmic {
+sandbox_pmic@40 {
compatible = "sandbox,pmic";
reg = <0x40>;
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index e3229ef..e3e2835 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1038,11 +1038,11 @@ int cros_ec_decode_ec_flash(const void *blob, int node,
const char *name = fdt_get_name(blob, node, NULL);
enum ec_flash_region region;
- if (0 == strcmp(name, "ro")) {
+ if (0 == strcmp(name, "ro@0")) {
region = EC_FLASH_REGION_RO;
- } else if (0 == strcmp(name, "rw")) {
+ } else if (0 == strcmp(name, "rw@10000")) {
region = EC_FLASH_REGION_RW;
- } else if (0 == strcmp(name, "wp-ro")) {
+ } else if (0 == strcmp(name, "wp-ro@f000")) {
region = EC_FLASH_REGION_WP_RO;
} else {
debug("Unknown EC flash region name '%s'\n", name);
