Fix up eSDHC controller clock frequency in the device tree for P1 & P2 RDB
platforms
Signed-off-by: Dipen Dudhat <dipen.dud...@freescale.com>
---
- applies on git.denx.de/u-boot-mpc85xx.git branch->next
board/freescale/p1_p2_rdb/p1_p2_rdb.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 4c03468..4d99e43 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -209,6 +209,9 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#ifdef CONFIG_FSL_ESDHC
+ fdt_fixup_esdhc(blob, bd);
+#endif
}
#endif
--
1.5.6.3
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