When MMU is disabled, 64bit Write must be at a memory aligned at 64-bit
Boundary. So, this commit splits the 64-bit write into two 32-bit writes
as the memory location is not guaranteed to be 64-bit aligned. The
alignment exception only occurs when MMU is disabled.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
---
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- No changes
Changes for v5:
- Cleaned up commit message
drivers/crypto/fsl/desc_constr.h | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index 2559ccd..db6ddee 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -85,10 +85,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
#ifdef CONFIG_PHYS_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
- union ptr_addr_t ptr_addr;
- ptr_addr.m_halfs.high = (u32)(ptr >> 32);
- ptr_addr.m_halfs.low = (u32)ptr;
- *offset = ptr_addr.m_whole;
+ union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
+ ptr_addr->m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr->m_halfs.low = (u32)ptr;
#else
*offset = ptr;
#endif
--
1.8.1.4
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