Hello,
We are currently designing a board based on the T1040 CPU from Freescale/NXP. I
am preparing its u-boot support and bring-up tools (JTAG) as well as
contributing to the hardware design. We base our work (both HW and SW) on the
1040RDB dev board as our reference design. We want to use a parallel
("classical", not SPI) NOR Flash to boot from and to store our RCW/PBL and
u-boot.
I have a question regarding the Boot location address when booting from the NOR
flash. From the documentation, it is clear that the RCW and PBL instructions are
read from the NOR (when cfg_rcw_src and RCW[PBI_SRC] are defined accordingly)
through CS0 at from the address 0x0000_0000 (RM 27.5.1, PBL Starting addresses).
I have not found a clear indication about this in the doc, but I guess that the
PBL manages to minimally configure the IFC NOR controller to make sure the
addresses it accesses trigger the CS0 and drives the address lines to access
address 0 and counting up. My understanding is that we must thus make sure that
the NOR Flash's CS is connected to the CS0.
For the actual boot location (i.e. when the cores start to execute code, after
the RCW/PBL sequence), as stated in section 4.3.3 in the RM (Boot Space
Translation), the cores execute the code that is located in the 4K page located
at address 0x0_FFFF_F000, starting with the reset vector at address
0x0_FFFF_FFFC, which are located in the default boot location (0x0_FF80_0000 to
0x0_FFFF_FFFF). My conclusion is that somehow, the IFC NOR controller is again
configured so that the accesses to this memory range will trigger the CS0 NOR
access (in the T1040RDB RCW/PBL, I have seen no indication that another boot
window than the default one is use, since the boot space translation capability
is unused). But since the NOR boot section (24.6.1) does not give any details, I
have no idea how this works.
Now u-boot, for its T1040RDB support, uses a memory mapping for the NOR Flash
that is not aligned with the above boot location mapping. The 128 MB of the NOR
flash are mapped from 0xE800_0000 to 0xEFFF_FFFF. My guess about this "change"
it that it is to avoid the memory conflict with CCSR that is located at
0x0_FE00_0000 by default when the NOR is bigger than 16 MB. I think this mapping
is only relevant later in the u-boot boot sequence, when the TLBs and LAWs are
configured but not at boot time.
I have two questions about this NOR boot mechanism:
- how are the NOR accesses really happening (or how is the IFC NOR configured)
at boot time to read the RCW/PBL and the boot code at boot location ? I ask this
in order to make sure that our HW design will allow us to boot from the NOR
Flash (i.e. how we connect the NOR address bus to the IFC)
- what about CONFIG_SYS_TEXT_BASE ? I see that it defined according the later
"u-boot" memory mapping. Why this one and not the "boot time" one ?
Thanks your answers
Valentin
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