On 03/16/2016 09:59 AM, Wills Wang wrote: > This patch enable work for ar933x SOC. > > Signed-off-by: Wills Wang <wills.w...@live.com> > --- > > Changes in v8: > - Fix multi-line comment for ar933x > > Changes in v7: > - Use CKSEGxADDR instead of KSEGxADDR for ar933x > > Changes in v6: > - Remove board.c > - Define magic value in ddr.c > > Changes in v5: > - Add ddr.c for ar933x > > Changes in v4: > - Add clk.c for ar933x > > Changes in v3: None > Changes in v2: None
[...] > +#define DDR_REFRESH_EN (1 << 14) > +#define DDR_REFRESH_M 0x3ff > +#define DDR_REFRESH(x) ((x) & 0x3ff) > +#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390)) > +#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624)) > + > +#define DDR_TRAS_S 0 > +#define DDR_TRAS_M 0x1f > +#define DDR_TRAS(x) ((x) << DDR_TRAS_S) > +#define DDR_TRCD_M 0xf > +#define DDR_TRCD_S 5 > +#define DDR_TRCD(x) ((x) << DDR_TRCD_S) > +#define DDR_TRP_M 0xf > +#define DDR_TRP_S 9 > +#define DDR_TRP(x) ((x) << DDR_TRP_S) > +#define DDR_TRRD_M 0xf > +#define DDR_TRRD_S 13 > +#define DDR_TRRD(x) ((x) << DDR_TRRD_S) > +#define DDR_TRFC_M 0x7f > +#define DDR_TRFC_S 17 > +#define DDR_TRFC(x) ((x) << DDR_TRFC_S) > +#define DDR_TMRD_M 0xf > +#define DDR_TMRD_S 23 > +#define DDR_TMRD(x) ((x) << DDR_TMRD_S) > +#define DDR_CAS_L_M 0x17 > +#define DDR_CAS_L_S 27 > +#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S) > +#define DDR_OPEN (1 << 30) Use the BIT() macro consistently ;-) > +#define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \ > + DDR_TRP(6) | DDR_TRRD(4) | \ > + DDR_TRFC(30) | DDR_TMRD(15) | \ > + DDR_CAS_L(7) | DDR_OPEN) > + [...] -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
