These settings control the clocks around the memory controller.
The debug ability is unneeded once it works properly.
Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
---
arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
index c28492c..f89b1da 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
@@ -24,9 +24,9 @@ static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617,
0x00770617};
static void umc_start_ssif(void __iomem *ssif_base)
{
- writel(0x00000001, ssif_base + 0x0000b004);
+ writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x07ffffff, ssif_base + 0x0000c008);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
--
1.9.1
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