On 02/01/2016 07:36 PM, Mingkai Hu wrote: > From: Mingkai Hu <mingkai...@nxp.com> > > Memory controller performance is not optimal with default internal > target queue register value, write required value for optimal DDR > performance. > > Signed-off-by: Mingkai Hu <mingkai...@nxp.com> > --- > v3: > - Move the macro check to soc.c. > > v2: > - Add a check to make sure A009660 and A008514 is are not both enabled. > - Add comment for the offset of eddrtqcr1. > > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 19 +++++++++++++++++++ > arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + > 2 files changed, 20 insertions(+) >
Applied to fsl-qoriq master. Awaiting upstream. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
