From: Lin Huang <h...@rock-chips.com>

emac may use dpll as clock parent, and it request the clock frequency
multiples of 50, so change ddr frequency to 400M.

Signed-off-by: Lin Huang <h...@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.c...@rock-chips.com>

---

 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c 
b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index e3ca870..ec8305c 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -37,7 +37,7 @@ struct rk3036_sdram_priv {
 /* use integer mode, 396MHz dpll setting
  * refdiv, fbdiv, postdiv1, postdiv2
  */
-const struct pll_div dpll_init_cfg = {1, 66, 4, 1};
+const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
 
 /* 396Mhz ddr timing */
 const struct rk3036_ddr_timing ddr_timing = {0x18c,
-- 
2.1.4


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