Add a driver with an empty probe function where we can move init code in
follow-on patches.
Signed-off-by: Simon Glass <s...@chromium.org>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
---
Changes in v2: None
arch/x86/cpu/ivybridge/early_init.c | 18 ++++++++++++++++++
arch/x86/dts/chromebook_link.dts | 7 +++++++
2 files changed, 25 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/early_init.c
b/arch/x86/cpu/ivybridge/early_init.c
index 9ca008e..945ae2d 100644
--- a/arch/x86/cpu/ivybridge/early_init.c
+++ b/arch/x86/cpu/ivybridge/early_init.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
@@ -145,3 +146,20 @@ void sandybridge_early_init(int chipset_type)
sandybridge_setup_graphics(pch_dev, video_dev);
}
+
+static int bd82x6x_northbridge_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct udevice_id bd82x6x_northbridge_ids[] = {
+ { .compatible = "intel,bd82x6x-northbridge" },
+ { }
+};
+
+U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
+ .name = "bd82x6x_northbridge",
+ .id = UCLASS_NORTHBRIDGE,
+ .of_match = bd82x6x_northbridge_ids,
+ .probe = bd82x6x_northbridge_probe,
+};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index f2db844..e2c722d 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -166,6 +166,13 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
+
+ northbridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ compatible = "intel,bd82x6x-northbridge";
+ u-boot,dm-pre-reloc;
+ };
+
sata {
compatible = "intel,pantherpoint-ahci";
intel,sata-mode = "ahci";
--
2.6.0.rc2.230.g3dd15c0
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