On Sun, Dec 27, 2015 at 05:12:24AM +0200, Vladimir Zapolskiy wrote: > The change fixes PHY write operation, which incorrectly waits for > released busy state before issuing a write operation, this breaks > sequential write/read operation logic, because read operation > starts immediately on request and it completes, when busy state is > gone. > > Instead of adding the second preceding busy state check to read > function, do busy state release check after issuing a write operation, > this method of operation is also recommended by the LPC32xx User's > Manual, see MII Mgmt Indicators Register notes: > > For PHY Write if scan is not used: > 1. Write 0 to MCMD > 2. Write PHY address and register address to MADR > 3. Write data to MWTD > 4. Wait for busy bit to be cleared in MIND > > Reported-by: Alexandre Messier <amess...@tycoint.com> > Signed-off-by: Vladimir Zapolskiy <v...@mleia.com> > Tested-by: Alexandre Messier <amess...@tycoint.com>
Applied to u-boot/master, thanks! -- Tom
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