On 12 January 2016 at 03:18, Purna Chandra Mandal <purna.man...@microchip.com> wrote: > This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy > module. > DDR2 controller operates in half-rate mode (upto 533MHZ frequency). > > Signed-off-by: Paul Thacker <paul.thac...@microchip.com> > Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> > > > --- > > Changes in v3: > - annotating fixed table with const > - fix camel-case in ddr2 timing parameters > - fix cmd index parameter of host_load_cmd(). > - fix compilation warning > > Changes in v2: > - move ddr2 initialization from board/microchip/ to drivers/ddr/microchip > > arch/mips/mach-pic32/include/mach/ddr.h | 32 ++++ > drivers/Makefile | 1 + > drivers/ddr/microchip/Makefile | 6 + > drivers/ddr/microchip/ddr2.c | 278 > ++++++++++++++++++++++++++++++++ > drivers/ddr/microchip/ddr2_regs.h | 148 +++++++++++++++++ > drivers/ddr/microchip/ddr2_timing.h | 65 ++++++++ > 6 files changed, 530 insertions(+) > create mode 100644 arch/mips/mach-pic32/include/mach/ddr.h > create mode 100644 drivers/ddr/microchip/Makefile > create mode 100644 drivers/ddr/microchip/ddr2.c > create mode 100644 drivers/ddr/microchip/ddr2_regs.h > create mode 100644 drivers/ddr/microchip/ddr2_timing.h
Reviewed-by: Simon Glass <s...@chromium.org> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
