Used dwc2 usb otg device driver frame and added USB PHY handle function.
Signed-off-by: Frank Wang <frank.w...@rock-chips.com>
---
board/evb_rk3036/evb_rk3036/evb_rk3036.c | 30 +++++++++++++++++++
drivers/usb/gadget/Makefile | 1 +
drivers/usb/gadget/dwc2_udc_otg_regs.h | 5 ++++
drivers/usb/gadget/rk_otg_phy.c | 48 ++++++++++++++++++++++++++++++
include/configs/rk3036_common.h | 20 +++++++++++++
5 files changed, 104 insertions(+)
create mode 100644 drivers/usb/gadget/rk_otg_phy.c
diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c
b/board/evb_rk3036/evb_rk3036/evb_rk3036.c
index f5758b1..ec3f973 100644
--- a/board/evb_rk3036/evb_rk3036/evb_rk3036.c
+++ b/board/evb_rk3036/evb_rk3036/evb_rk3036.c
@@ -10,6 +10,11 @@
#include <asm/arch/uart.h>
#include <asm/arch/sdram_rk3036.h>
+#ifdef CONFIG_USB_GADGET
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
void get_ddr_config(struct rk3036_ddr_config *config)
@@ -47,3 +52,28 @@ void enable_caches(void)
dcache_enable();
}
#endif
+
+#ifdef CONFIG_USB_GADGET
+#define RKIO_GRF_PHYS 0x20008000
+#define RKIO_USBOTG_BASE 0x10180000
+#define RK_USB_PHY_CONTROL 0x10180e00
+
+static struct dwc2_plat_otg_data rk_otg_data = {
+ .regs_phy = RKIO_GRF_PHYS,
+ .regs_otg = RKIO_USBOTG_BASE,
+ .usb_phy_ctrl = RK_USB_PHY_CONTROL,
+ .usb_gusbcfg = 0x00001408
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("%s: performing dwc2_udc_probe\n", __func__);
+ return dwc2_udc_probe(&rk_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ debug("%s\n", __func__);
+ return 0;
+}
+#endif
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index c915c79..54eb89b 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o
obj-$(CONFIG_USB_FUNCTION_DFU) += f_dfu.o
obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o
+obj-$(CONFIG_USB_GADGET_RK_OTG_PHY) += rk_otg_phy.o
endif
ifdef CONFIG_USB_ETHER
obj-y += ether.o
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h
b/drivers/usb/gadget/dwc2_udc_otg_regs.h
index 78ec90e..34a29be 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_regs.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
@@ -130,8 +130,13 @@ struct dwc2_usbotg_reg {
#define HIGH_SPEED_CONTROL_PKT_SIZE 64
#define HIGH_SPEED_BULK_PKT_SIZE 512
+#ifndef CONFIG_ARCH_ROCKCHIP
#define RX_FIFO_SIZE (1024*4)
#define NPTX_FIFO_SIZE (1024*4)
+#else
+#define RX_FIFO_SIZE ((512+16)*4)
+#define NPTX_FIFO_SIZE (64)
+#endif
#define PTX_FIFO_SIZE (1536*1)
#define DEPCTL_TXFNUM_0 (0x0<<22)
diff --git a/drivers/usb/gadget/rk_otg_phy.c b/drivers/usb/gadget/rk_otg_phy.c
new file mode 100644
index 0000000..af45555
--- /dev/null
+++ b/drivers/usb/gadget/rk_otg_phy.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "dwc2_udc_otg_regs.h"
+#include "dwc2_udc_otg_priv.h"
+
+/* UOC control */
+#define GRF_UOC0_CON5 0x017c
+
+void otg_phy_init(struct dwc2_udc *dev)
+{
+ struct dwc2_usbotg_reg *reg =
+ (struct dwc2_usbotg_reg *)dev->pdata->regs_otg;
+
+ /* Disable usb-uart bypass */
+ writel(0x34000000, (dev->pdata->regs_phy + GRF_UOC0_CON5));
+
+ /* soft disconnect */
+ writel(readl(®->dctl) | ~0x02, ®->dctl);
+
+ /* Phy PLL recovering */
+ writel(0x00030001, (dev->pdata->regs_phy + GRF_UOC0_CON5));
+ udelay(15);
+ writel(0x00030002, (dev->pdata->regs_phy + GRF_UOC0_CON5));
+ udelay(1500);
+
+ /* Restart the Phy Clock */
+ writel(0x00, (u32 *)dev->pdata->usb_phy_ctrl);
+
+ /* soft connect */
+ writel(readl(®->dctl) & ~0x02, ®->dctl);
+}
+
+void otg_phy_off(struct dwc2_udc *dev)
+{
+ /* usbphy0 bypass disable and otg enable */
+ writel(0x34000000, (dev->pdata->regs_phy + GRF_UOC0_CON5));
+
+ /* usb phy enter suspend */
+ writel(0x007f0055, (dev->pdata->regs_phy + GRF_UOC0_CON5));
+}
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index f753e68..d804b60 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -71,6 +71,26 @@
#define CONFIG_CMD_I2C
+/* FASTBOOT */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_USB_GADGET_RK_OTG_PHY
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
+#define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \
+ + SDRAM_BANK_SIZE)
+#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
+#define CONFIG_USB_GADGET_VBUS_DRAW 0
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM 0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM 0x0006
+
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
--
1.7.9.5
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