This is a small series to move the ICH driver over to use the driver model
PCI API. It involves creating PCH drivers which the ICH driver can use to
find out its base address.
At present irq-router is the 'PCH' node in most device tree files. This is
not really correct since the router is just one of the functions of the PCH.
Another is the SPI bus. So this series also moves irq-router down a level.
This still works with the same irq-router driver, since it just searches for
the first compatible node it can find.
A driver-model-compatible irq-router driver should be written but that is
left for later.
This series unfortunately needs testing on each board since each has a
separate change. I have tested minnowmax and chromebook_link so far.
Changes in v3:
- Add a PCH method to enable/disable SPI flash protection
- Drop the pch_init() call
- Add a new patch to separate out the read/write trace from normal debugging
- Use the set_spi_protect() PCH method
Changes in v2:
- Add more detail to the function comment
- Rename the last parameter to 'addr'
- Update the comment to explain usable of this function
- Update the commit message and header file comments
- Use an enum for the PCH version
- Replace SBASE with SPI base
- Add a TODO to check if the init() method can be removed later
- Rename the PCH functions
- Update the get_version() handle to use an enum
- Add a function to obtain the SPI base address
- Add enums for BIOS_CTRL register and bits
- Rename the PCH functions
- Update the get_version() handle to use an enum
- Adjust code for earlier commits
- Move the SPI base code into the PCH drivers
Simon Glass (8):
dm: pci: Move pci_bus_to_hose() to compatibility
dm: pci: Add a function to write a BAR
dm: pci: Avoid using pci_bus_to_hose() in the uclass
dm: Expand the uclass for Platform Controller Hubs (PCH)
dm: x86: Add a driver for Intel PCH7
dm: x86: Add a driver for Intel PCH9
spi: ich: Separate out the read/write trace from normal debugging
dm: x86: spi: Convert ICH SPI driver to driver model PCI API
arch/x86/cpu/coreboot/pci.c | 3 +-
arch/x86/cpu/irq.c | 7 +-
arch/x86/cpu/ivybridge/bd82x6x.c | 45 +++++++-
arch/x86/dts/bayleybay.dts | 160 +++++++++++++-------------
arch/x86/dts/broadwell_som-6896.dts | 23 ++--
arch/x86/dts/chromebook_link.dts | 5 +-
arch/x86/dts/chromebox_panther.dts | 33 +++---
arch/x86/dts/crownbay.dts | 150 ++++++++++++------------
arch/x86/dts/galileo.dts | 98 ++++++++--------
arch/x86/dts/minnowmax.dts | 158 ++++++++++++++------------
arch/x86/dts/qemu-x86_i440fx.dts | 26 +++--
arch/x86/dts/qemu-x86_q35.dts | 38 ++++---
arch/x86/lib/Makefile | 1 -
drivers/Makefile | 1 +
drivers/pch/Makefile | 7 ++
{arch/x86/lib => drivers/pch}/pch-uclass.c | 32 ++++++
drivers/pch/pch7.c | 59 ++++++++++
drivers/pch/pch9.c | 43 +++++++
drivers/pci/pci-uclass.c | 24 ++--
drivers/pci/pci_auto.c | 14 +--
drivers/pci/pci_compat.c | 15 +++
drivers/pci/pci_internal.h | 12 ++
drivers/spi/ich.c | 176 +++++++++--------------------
include/pch.h | 83 ++++++++++++++
include/pci.h | 17 ++-
25 files changed, 754 insertions(+), 476 deletions(-)
create mode 100644 drivers/pch/Makefile
rename {arch/x86/lib => drivers/pch}/pch-uclass.c (50%)
create mode 100644 drivers/pch/pch7.c
create mode 100644 drivers/pch/pch9.c
create mode 100644 include/pch.h
--
2.6.0.rc2.230.g3dd15c0
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