On 12/16/2015 04:02 PM, Shengzhou Liu wrote: > Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 > before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] > to the desired value after DDR initialization has completed. > > Signed-off-by: Shengzhou Liu <shengzhou....@freescale.com> > --- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ > arch/arm/include/asm/arch-ls102xa/config.h | 1 + > arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ > arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ > drivers/ddr/fsl/fsl_ddr_gen4.c | 10 ++++++++++ > include/fsl_ddr_sdram.h | 1 + > 6 files changed, 20 insertions(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > index 6e5224e..fac82ff 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -118,6 +118,8 @@ > #define CONFIG_SYS_FSL_ERRATUM_A008585 > #define CONFIG_SYS_FSL_ERRATUM_A008751 > #define CONFIG_SYS_FSL_ERRATUM_A009635 > +#define CONFIG_SYS_FSL_ERRATUM_A009663 > + > #elif defined(CONFIG_LS1043A) > #define CONFIG_MAX_CPUS 4 > #define CONFIG_SYS_CACHELINE_SIZE 64 > @@ -165,6 +167,7 @@ > /* Generic Interrupt Controller Definitions */ > #define GICD_BASE 0x01401000 > #define GICC_BASE 0x01402000 > +#define CONFIG_SYS_FSL_ERRATUM_A009663 > > #else > #error SoC not defined > diff --git a/arch/arm/include/asm/arch-ls102xa/config.h > b/arch/arm/include/asm/arch-ls102xa/config.h > index f066480..424fe87 100644 > --- a/arch/arm/include/asm/arch-ls102xa/config.h > +++ b/arch/arm/include/asm/arch-ls102xa/config.h > @@ -131,6 +131,7 @@ > #define CONFIG_SYS_FSL_SEC_COMPAT 5 > #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 > #define CONFIG_SYS_FSL_ERRATUM_A008378 > +#define CONFIG_SYS_FSL_ERRATUM_A009663 > #else > #error SoC not defined > #endif > diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c > b/arch/powerpc/cpu/mpc85xx/cmd_errata.c > index a493556..3b06ae4 100644 > --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c > +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c > @@ -326,6 +326,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int > argc, char * const argv[]) > #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) > puts("Work-around for Erratum XFI on B4860QDS enabled\n"); > #endif > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 > + puts("Work-around for Erratum A009663 enabled\n"); > +#endif > > return 0; > } > diff --git a/arch/powerpc/include/asm/config_mpc85xx.h > b/arch/powerpc/include/asm/config_mpc85xx.h > index 674fac8..eccc146 100644 > --- a/arch/powerpc/include/asm/config_mpc85xx.h > +++ b/arch/powerpc/include/asm/config_mpc85xx.h > @@ -808,6 +808,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) > #define QE_NUM_OF_SNUM 28 > #define CONFIG_SYS_FSL_SFP_VER_3_0 > #define CONFIG_SYS_FSL_ERRATUM_A008378 > +#define CONFIG_SYS_FSL_ERRATUM_A009663 > > #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ > defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) > @@ -856,6 +857,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) > #define QE_NUM_OF_SNUM 28 > #define CONFIG_SYS_FSL_SFP_VER_3_0 > #define CONFIG_SYS_FSL_ERRATUM_A008378 > +#define CONFIG_SYS_FSL_ERRATUM_A009663 > > #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) > #define CONFIG_E6500 > diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c > index 3fca5c2..6bd447d 100644 > --- a/drivers/ddr/fsl/fsl_ddr_gen4.c > +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c > @@ -151,7 +151,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t > *regs, > ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); > ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); > ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 > + ddr_out32(&ddr->sdram_interval, > + regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); > +#else > ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); > +#endif
Please add some comment to explain when BSTOPRE is zero (auto), this workaround is not needed. So users understand why it has been working so far. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot