Hi Dennis, On Sun, Dec 13, 2015 at 11:33:46AM -0600, Dennis Gilmore wrote: > Trying to test this I have hit an error with CONFIG_PHY_ADDR not defined. > > I am guessing that I am missing some other sets of patches. digging through > patchwork I am not able to figure it out. there is a bunch of patches in > patchwork that say they are in NEW state however they are in the tree so not > labeled correctly. Any clues as to which patch sets this depends on are > appreciated.
I've asked Stefan to put the patches up on some git repo for easier review and pull on my side. I'm also very eager to test this patchset! Regards, Luka > Dennis > > > On Friday, November 27, 2015 04:15:17 PM Stefan Roese wrote: > > This patch adds basic support for the SolidRun ClearFog Armada 38x based > > board to mainline U-Boot. Supported interfaces / devices are: > > - DDR3 > > - UART > > - MMC > > - Ethernet port 0 (connected to dedicated PHY) > > - I2C > > > > The included DT source was taken from Russell King's ftp server: > > http://www.home.arm.linux.org.uk/~rmk/clearfog/ > > > > With only minor modifications, like the addition of some aliases and the > > "u-boot,dm-pre-reloc" property. > > > > Signed-off-by: Stefan Roese <s...@denx.de> > > Cc: Rabeeh Khoury <rab...@solid-run.com> > > Cc: Luka Perkov <luka.per...@sartura.hr> > > --- > > arch/arm/Kconfig | 1 + > > arch/arm/dts/Makefile | 1 + > > arch/arm/dts/armada-388-clearfog.dts | 509 > > +++++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | > > 3 + > > board/solidrun/clearfog/Kconfig | 12 + > > board/solidrun/clearfog/MAINTAINERS | 6 + > > board/solidrun/clearfog/Makefile | 7 + > > board/solidrun/clearfog/README | 18 ++ > > board/solidrun/clearfog/clearfog.c | 156 +++++++++++ > > board/solidrun/clearfog/kwbimage.cfg | 12 + > > configs/clearfog_defconfig | 20 ++ > > include/configs/clearfog.h | 183 +++++++++++++ > > 12 files changed, 928 insertions(+) > > create mode 100644 arch/arm/dts/armada-388-clearfog.dts > > create mode 100644 board/solidrun/clearfog/Kconfig > > create mode 100644 board/solidrun/clearfog/MAINTAINERS > > create mode 100644 board/solidrun/clearfog/Makefile > > create mode 100644 board/solidrun/clearfog/README > > create mode 100644 board/solidrun/clearfog/clearfog.c > > create mode 100644 board/solidrun/clearfog/kwbimage.cfg > > create mode 100644 configs/clearfog_defconfig > > create mode 100644 include/configs/clearfog.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 4ddc2de..0c4794b 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -801,6 +801,7 @@ source "board/siemens/draco/Kconfig" > > source "board/siemens/pxm2/Kconfig" > > source "board/siemens/rut/Kconfig" > > source "board/silica/pengwyn/Kconfig" > > +source "board/solidrun/clearfog/Kconfig" > > source "board/spear/spear300/Kconfig" > > source "board/spear/spear310/Kconfig" > > source "board/spear/spear320/Kconfig" > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > > index 9719103..0494997 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -47,6 +47,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ > > tegra210-p2571.dtb > > > > dtb-$(CONFIG_ARCH_MVEBU) += \ > > + armada-388-clearfog.dtb \ > > armada-388-gp.dtb \ > > armada-xp-gp.dtb \ > > armada-xp-maxbcm.dtb > > diff --git a/arch/arm/dts/armada-388-clearfog.dts > > b/arch/arm/dts/armada-388-clearfog.dts new file mode 100644 > > index 0000000..b2dfd56 > > --- /dev/null > > +++ b/arch/arm/dts/armada-388-clearfog.dts > > @@ -0,0 +1,509 @@ > > +/* > > + * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828) > > + * > > + * Copyright (C) 2015 Russell King > > + * > > + * This board is in development; the contents of this file work with > > + * the A1 rev 2.0 of the board, which does not represent final > > + * production board. Things will change, don't expect this file to > > + * remain compatible info the future. > > + * > > + * This file is dual-licensed: you can use it either under the terms > > + * of the GPL or the X11 license, at your option. Note that this dual > > + * licensing only applies to this file, and not this project as a > > + * whole. > > + * > > + * a) This file is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License > > + * version 2 as published by the Free Software Foundation. > > + * > > + * This file is distributed in the hope that it will be useful > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * Or, alternatively > > + * > > + * b) Permission is hereby granted, free of charge, to any person > > + * obtaining a copy of this software and associated documentation > > + * files (the "Software"), to deal in the Software without > > + * restriction, including without limitation the rights to use > > + * copy, modify, merge, publish, distribute, sublicense, and/or > > + * sell copies of the Software, and to permit persons to whom the > > + * Software is furnished to do so, subject to the following > > + * conditions: > > + * > > + * The above copyright notice and this permission notice shall be > > + * included in all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND > > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY > > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > > + * OTHER DEALINGS IN THE SOFTWARE. > > + */ > > + > > +/dts-v1/; > > +#include <dt-bindings/input/input.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include "armada-388.dtsi" > > + > > +/ { > > + model = "SolidRun Clearfog A1"; > > + compatible = "solidrun,clearfog-a1", "marvell,armada388", > > + "marvell,armada385", "marvell,armada380"; > > + > > + aliases { > > + /* So that mvebu u-boot can update the MAC addresses */ > > + ethernet1 = ð0; > > + ethernet2 = ð1; > > + ethernet3 = ð2; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory { > > + device_type = "memory"; > > + reg = <0x00000000 0x10000000>; /* 256 MB */ > > + }; > > + > > + reg_3p3v: regulator-3p3v { > > + compatible = "regulator-fixed"; > > + regulator-name = "3P3V"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + regulator-always-on; > > + }; > > + > > + soc { > > + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 > > + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 > > + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 > > + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; > > + > > + internal-regs { > > + ethernet@30000 { > > + mac-address = [00 50 43 02 02 02]; > > + phy-mode = "sgmii"; > > + status = "okay"; > > + > > + fixed-link { > > + speed = <1000>; > > + full-duplex; > > + }; > > + }; > > + > > + ethernet@34000 { > > + mac-address = [00 50 43 02 02 03]; > > + managed = "in-band-status"; > > + phy-mode = "sgmii"; > > + status = "okay"; > > + }; > > + > > + ethernet@70000 { > > + mac-address = [00 50 43 02 02 01]; > > + pinctrl-0 = <&ge0_rgmii_pins>; > > + pinctrl-names = "default"; > > + phy = <&phy_dedicated>; > > + phy-mode = "rgmii-id"; > > + status = "okay"; > > + }; > > + > > + i2c@11000 { > > + /* Is there anything on this? */ > > + clock-frequency = <100000>; > > + pinctrl-0 = <&i2c0_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + > > + /* > > + * PCA9655 GPIO expander, up to 1MHz clock. > > + * 0-CON3 CLKREQ# > > + * 1-CON3 PERST# > > + * 2-CON2 PERST# > > + * 3-CON3 W_DISABLE > > + * 4-CON2 CLKREQ# > > + * 5-USB3 overcurrent > > + * 6-USB3 power > > + * 7-CON2 W_DISABLE > > + * 8-JP4 P1 > > + * 9-JP4 P4 > > + * 10-JP4 P5 > > + * 11-m.2 DEVSLP > > + * 12-SFP_LOS > > + * 13-SFP_TX_FAULT > > + * 14-SFP_TX_DISABLE > > + * 15-SFP_MOD_DEF0 > > + */ > > + expander0: gpio-expander@20 { > > + /* > > + * This is how it should be: > > + * compatible = "onnn,pca9655", > > + * "nxp,pca9555"; > > + * but you can't do this because of > > + * the way I2C works. > > + */ > > + compatible = "nxp,pca9555"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + reg = <0x20>; > > + > > + pcie1_0_clkreq { > > + gpio-hog; > > + gpios = <0 GPIO_ACTIVE_LOW>; > > + input; > > + line-name = "pcie1.0-clkreq"; > > + }; > > + pcie1_0_w_disable { > > + gpio-hog; > > + gpios = <3 GPIO_ACTIVE_LOW>; > > + output-low; > > + line-name = "pcie1.0-w-disable"; > > + }; > > + pcie2_0_clkreq { > > + gpio-hog; > > + gpios = <4 GPIO_ACTIVE_LOW>; > > + input; > > + line-name = "pcie2.0-clkreq"; > > + }; > > + pcie2_0_w_disable { > > + gpio-hog; > > + gpios = <7 GPIO_ACTIVE_LOW>; > > + output-low; > > + line-name = "pcie2.0-w-disable"; > > + }; > > + usb3_ilimit { > > + gpio-hog; > > + gpios = <5 GPIO_ACTIVE_LOW>; > > + input; > > + line-name = > > "usb3-current-limit"; > > + }; > > + usb3_power { > > + gpio-hog; > > + gpios = <6 GPIO_ACTIVE_HIGH>; > > + output-high; > > + line-name = "usb3-power"; > > + }; > > + m2_devslp { > > + gpio-hog; > > + gpios = <11 GPIO_ACTIVE_HIGH>; > > + output-low; > > + line-name = "m.2 devslp"; > > + }; > > + }; > > + > > + /* The MCP3021 is 100kHz clock only */ > > + mikrobus_adc: mcp3021@4c { > > + compatible = "microchip,mcp3021"; > > + reg = <0x4c>; > > + }; > > + > > + /* Also something at 0x64 */ > > + }; > > + > > + i2c@11100 { > > + /* > > + * Routed to SFP, mikrobus, and PCIe. > > + * SFP limits this to 100kHz, and requires > > + * an AT24C01A/02/04 with address pins tied > > + * low, which takes addresses 0x50 and 0x51. > > + * Mikrobus doesn't specify beyond an I2C > > + * bus being present. > > + * PCIe uses ARP to assign addresses, or > > + * 0x63-0x64. > > + */ > > + clock-frequency = <100000>; > > + pinctrl-0 = <&clearfog_i2c1_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + }; > > + > > + mdio@72004 { > > + pinctrl-0 = <&mdio_pins>; > > + pinctrl-names = "default"; > > + > > + phy_dedicated: ethernet-phy@0 { > > + /* > > + * Annoyingly, the marvell phy driver > > + * configures the LED register, rather > > + * than preserving reset-loaded setting. > > + * We undo that rubbish here. > > + */ > > + marvell,reg-init = <3 16 0 0x101e>; > > + reg = <0>; > > + }; > > + }; > > + > > + pinctrl@18000 { > > + clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { > > + marvell,pins = "mpp46"; > > + marvell,function = "ref"; > > + }; > > + clearfog_dsa0_pins: clearfog-dsa0-pins { > > + marvell,pins = "mpp23", "mpp41"; > > + marvell,function = "gpio"; > > + }; > > + clearfog_i2c1_pins: i2c1-pins { > > + /* SFP, PCIe, mSATA, mikrobus */ > > + marvell,pins = "mpp26", "mpp27"; > > + marvell,function = "i2c1"; > > + }; > > + clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { > > + marvell,pins = "mpp20"; > > + marvell,function = "gpio"; > > + }; > > + clearfog_sdhci_pins: clearfog-sdhci-pins { > > + marvell,pins = "mpp21", "mpp28", > > + "mpp37", "mpp38", > > + "mpp39", "mpp40"; > > + marvell,function = "sd0"; > > + }; > > + clearfog_spi1_cs_pins: spi1-cs-pins { > > + marvell,pins = "mpp55"; > > + marvell,function = "spi1"; > > + }; > > + mikro_pins: mikro-pins { > > + /* int: mpp22 rst: mpp29 */ > > + marvell,pins = "mpp22", "mpp29"; > > + marvell,function = "gpio"; > > + }; > > + mikro_spi_pins: mikro-spi-pins { > > + marvell,pins = "mpp43"; > > + marvell,function = "spi1"; > > + }; > > + mikro_uart_pins: mikro-uart-pins { > > + marvell,pins = "mpp24", "mpp25"; > > + marvell,function = "ua1"; > > + }; > > + rear_button_pins: rear-button-pins { > > + marvell,pins = "mpp34"; > > + marvell,function = "gpio"; > > + }; > > + }; > > + > > + rtc@a3800 { > > + /* > > + * If the rtc doesn't work, run "date reset" > > + * twice in u-boot. > > + */ > > + status = "okay"; > > + }; > > + > > + sata@a8000 { > > + /* pinctrl? */ > > + status = "okay"; > > + }; > > + > > + sata@e0000 { > > + /* pinctrl? */ > > + status = "okay"; > > + }; > > + > > + sdhci@d8000 { > > + bus-width = <4>; > > + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; > > + no-1-8-v; > > + pinctrl-0 = <&clearfog_sdhci_pins > > + &clearfog_sdhci_cd_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + vmmc = <®_3p3v>; > > + wp-inverted; > > + }; > > + > > + serial@12000 { > > + pinctrl-0 = <&uart0_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + u-boot,dm-pre-reloc; > > + }; > > + > > + serial@12100 { > > + /* mikrobus uart */ > > + pinctrl-0 = <&mikro_uart_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + }; > > + > > + spi@10680 { > > + /* > > + * We don't seem to have the W25Q32 on the > > + * A1 Rev 2.0 boards, so disable SPI. > > + * CS0: W25Q32 (doesn't appear to be present) > > + * CS1: > > + * CS2: mikrobus > > + */ > > + pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins > > &mikro_spi_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + > > + spi-flash@0 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "w25q32", "jedec,spi-nor"; > > + reg = <0>; /* Chip select 0 */ > > + spi-max-frequency = <3000000>; > > + status = "disabled"; > > + }; > > + }; > > + > > + usb3@f8000 { > > + status = "okay"; > > + }; > > + }; > > + > > + pcie-controller { > > + status = "okay"; > > + /* > > + * The two PCIe units are accessible through > > + * the mini-PCIe connectors on the board. > > + */ > > + pcie@2,0 { > > + /* Port 1, Lane 0. CONN3, nearest power. */ > > + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; > > + status = "okay"; > > + }; > > + pcie@3,0 { > > + /* Port 2, Lane 0. CONN2, nearest CPU. */ > > + reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; > > + status = "okay"; > > + }; > > + }; > > + }; > > + > > + sfp: sfp { > > + compatible = "sff,sfp"; > > + i2c-bus = <&i2c1>; > > + los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; > > + moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; > > + sfp,ethernet = <ð2>; > > + tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; > > + tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; > > + }; > > + > > + dsa@0 { > > + compatible = "marvell,dsa"; > > + dsa,ethernet = <ð1>; > > + dsa,mii-bus = <&mdio>; > > + pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; > > + pinctrl-names = "default"; > > + #address-cells = <2>; > > + #size-cells = <0>; > > + > > + switch@0 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <4 0>; > > + > > + port@0 { > > + reg = <0>; > > + label = "lan1"; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + label = "lan2"; > > + }; > > + > > + port@2 { > > + reg = <2>; > > + label = "lan3"; > > + }; > > + > > + port@3 { > > + reg = <3>; > > + label = "lan4"; > > + }; > > + > > + port@4 { > > + reg = <4>; > > + label = "lan5"; > > + }; > > + > > + port@5 { > > + reg = <5>; > > + label = "cpu"; > > + }; > > + > > + port@6 { > > + /* 88E1512 external phy */ > > + reg = <6>; > > + label = "lan6"; > > + fixed-link { > > + speed = <1000>; > > + full-duplex; > > + }; > > + }; > > + }; > > + }; > > + > > + gpio-keys { > > + compatible = "gpio-keys"; > > + pinctrl-0 = <&rear_button_pins>; > > + pinctrl-names = "default"; > > + > > + button_0 { > > + /* The rear SW3 button */ > > + label = "Rear Button"; > > + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; > > + linux,can-disable; > > + linux,code = <BTN_0>; > > + }; > > + }; > > +}; > > + > > +/* > > ++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 > > +MPP18: gpio ? (pca9655 int?) > > +MPP19: gpio ? (clkreq?) > > +MPP20: gpio ? (sd0 detect) > > +MPP21: sd0:cmd x sd0 > > +MPP22: gpio x mikro int > > +MPP23: gpio x switch irq > > ++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333 > > +MPP24: ua1:rxd x mikro rx > > +MPP25: ua1:txd x mikro tx > > +MPP26: i2c1:sck x mikro sck > > +MPP27: i2c1:sda x mikro sda > > +MPP28: sd0:clk x sd0 > > +MPP29: gpio x mikro rst > > +MPP30: ge1:txd2 ? (config) > > +MPP31: ge1:txd3 ? (config) > > ++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002 > > +MPP32: ge1:txctl ? (unused) > > +MPP33: gpio ? (pic_com0) > > +MPP34: gpio x rear button (pic_com1) > > +MPP35: gpio ? (pic_com2) > > +MPP36: gpio ? (unused) > > +MPP37: sd0:d3 x sd0 > > +MPP38: sd0:d0 x sd0 > > +MPP39: sd0:d1 x sd0 > > ++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004 > > +MPP40: sd0:d2 x sd0 > > +MPP41: gpio x switch reset > > +MPP42: gpio ? sw1-1 > > +MPP43: spi1:cs2 x mikro cs > > +MPP44: sata3:prsnt ? (unused) > > +MPP45: ref:clk_out0 ? > > +MPP46: ref:clk_out1 x switch clk > > +MPP47: 4 ? (unused) > > ++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333 > > +MPP48: tdm:pclk > > +MPP49: tdm:fsync > > +MPP50: tdm:drx > > +MPP51: tdm:dtx > > +MPP52: tdm:int > > +MPP53: tdm:rst > > +MPP54: gpio ? (pwm) > > +MPP55: spi1:cs1 x slic > > ++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444 > > +MPP56: spi1:mosi x mikro mosi > > +MPP57: spi1:sck x mikro sck > > +MPP58: spi1:miso x mikro miso > > +MPP59: spi1:cs0 x w25q32 > > +*/ > > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig > > index 79ff0e8..82a439e 100644 > > --- a/arch/arm/mach-mvebu/Kconfig > > +++ b/arch/arm/mach-mvebu/Kconfig > > @@ -4,6 +4,9 @@ choice > > prompt "Marvell MVEBU (Armada XP/38x) board select" > > optional > > > > +config TARGET_CLEARFOG > > + bool "Support ClearFog" > > + > > config TARGET_DB_88F6820_GP > > bool "Support DB-88F6820-GP" > > > > diff --git a/board/solidrun/clearfog/Kconfig > > b/board/solidrun/clearfog/Kconfig new file mode 100644 > > index 0000000..cdf8938 > > --- /dev/null > > +++ b/board/solidrun/clearfog/Kconfig > > @@ -0,0 +1,12 @@ > > +if TARGET_CLEARFOG > > + > > +config SYS_BOARD > > + default "clearfog" > > + > > +config SYS_VENDOR > > + default "solidrun" > > + > > +config SYS_CONFIG_NAME > > + default "clearfog" > > + > > +endif > > diff --git a/board/solidrun/clearfog/MAINTAINERS > > b/board/solidrun/clearfog/MAINTAINERS new file mode 100644 > > index 0000000..298e501 > > --- /dev/null > > +++ b/board/solidrun/clearfog/MAINTAINERS > > @@ -0,0 +1,6 @@ > > +CLEARFOG BOARD > > +M: Stefan Roese <s...@denx.de> > > +S: Maintained > > +F: board/soldrun/clearfog/ > > +F: include/configs/clearfog.h > > +F: configs/clearfog_defconfig > > diff --git a/board/solidrun/clearfog/Makefile > > b/board/solidrun/clearfog/Makefile new file mode 100644 > > index 0000000..1920d6b > > --- /dev/null > > +++ b/board/solidrun/clearfog/Makefile > > @@ -0,0 +1,7 @@ > > +# > > +# Copyright (C) 2015 Stefan Roese <s...@denx.de> > > +# > > +# SPDX-License-Identifier: GPL-2.0+ > > +# > > + > > +obj-y := clearfog.o > > diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README > > new file mode 100644 > > index 0000000..2cfa5bf > > --- /dev/null > > +++ b/board/solidrun/clearfog/README > > @@ -0,0 +1,18 @@ > > +Update from original Marvell U-Boot to mainline U-Boot: > > +------------------------------------------------------- > > + > > +Generate the U-Boot image with these commands: > > + > > +$ make clearfog_defconfig > > +$ make > > + > > +The resulting image including the SPL binary with the > > +full DDR setup is "u-boot-spl.kwb". > > + > > +Now all you need to do is copy this image on a SD card. > > +For example with this command: > > + > > +$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 > > + > > +Please use the correct device node for your setup instead > > +of "/dev/sdX" here! > > diff --git a/board/solidrun/clearfog/clearfog.c > > b/board/solidrun/clearfog/clearfog.c new file mode 100644 > > index 0000000..2773f59 > > --- /dev/null > > +++ b/board/solidrun/clearfog/clearfog.c > > @@ -0,0 +1,156 @@ > > +/* > > + * Copyright (C) 2015 Stefan Roese <s...@denx.de> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <i2c.h> > > +#include <miiphy.h> > > +#include <netdev.h> > > +#include <asm/io.h> > > +#include <asm/arch/cpu.h> > > +#include <asm/arch/soc.h> > > + > > +#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" > > +#include <../serdes/a38x/high_speed_env_spec.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +#define ETH_PHY_CTRL_REG 0 > > +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 > > +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << > > ETH_PHY_CTRL_POWER_DOWN_BIT) > > + > > +/* > > + * Those values and defines are taken from the Marvell U-Boot version > > + * "u-boot-2013.01-15t1-clearfog" > > + */ > > +#define BOARD_GPP_OUT_ENA_LOW 0xffffffff > > +#define BOARD_GPP_OUT_ENA_MID 0xffffffff > > + > > +#define BOARD_GPP_OUT_VAL_LOW 0x0 > > +#define BOARD_GPP_OUT_VAL_MID 0x0 > > +#define BOARD_GPP_POL_LOW 0x0 > > +#define BOARD_GPP_POL_MID 0x0 > > + > > +/* IO expander on Marvell GP board includes e.g. fan enabling */ > > +struct marvell_io_exp { > > + u8 chip; > > + u8 addr; > > + u8 val; > > +}; > > + > > +static struct marvell_io_exp io_exp[] = { > > + { 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */ > > + { 0x20, 6, 0xf9 }, > > + { 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */ > > + { 0x20, 6, 0xb9 }, > > + { 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */ > > + { 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */ > > +}; > > + > > +static struct serdes_map board_serdes_map[] = { > > + {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > > + {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > > + {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, > > + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > > + {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, > > + {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, > > +}; > > + > > +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 > > *count) +{ > > + *serdes_map_array = board_serdes_map; > > + *count = ARRAY_SIZE(board_serdes_map); > > + return 0; > > +} > > + > > +/* > > + * Define the DDR layout / topology here in the board file. This will > > + * be used by the DDR3 init code in the SPL U-Boot version to configure > > + * the DDR3 controller. > > + */ > > +static struct hws_topology_map board_topology_map = { > > + 0x1, /* active interfaces */ > > + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ > > + { { { {0x1, 0, 0, 0}, > > + {0x1, 0, 0, 0}, > > + {0x1, 0, 0, 0}, > > + {0x1, 0, 0, 0}, > > + {0x1, 0, 0, 0} }, > > + SPEED_BIN_DDR_1600K, /* speed_bin */ > > + BUS_WIDTH_16, /* memory_width */ > > + MEM_4G, /* mem_size */ > > + DDR_FREQ_800, /* frequency */ > > + 0, 0, /* cas_l cas_wl */ > > + HWS_TEMP_LOW} }, /* temperature */ > > + 5, /* Num Of Bus Per Interface*/ > > + BUS_MASK_32BIT /* Busses mask */ > > +}; > > + > > +struct hws_topology_map *ddr3_get_topology_map(void) > > +{ > > + /* Return the board topology as defined in the board code */ > > + return &board_topology_map; > > +} > > + > > +int board_early_init_f(void) > > +{ > > + /* Configure MPP */ > > + writel(0x11111111, MVEBU_MPP_BASE + 0x00); > > + writel(0x11111111, MVEBU_MPP_BASE + 0x04); > > + writel(0x10400011, MVEBU_MPP_BASE + 0x08); > > + writel(0x22043333, MVEBU_MPP_BASE + 0x0c); > > + writel(0x44400002, MVEBU_MPP_BASE + 0x10); > > + writel(0x41144004, MVEBU_MPP_BASE + 0x14); > > + writel(0x40333333, MVEBU_MPP_BASE + 0x18); > > + writel(0x00004444, MVEBU_MPP_BASE + 0x1c); > > + > > + /* Set GPP Out value */ > > + writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); > > + writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); > > + > > + /* Set GPP Polarity */ > > + writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); > > + writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); > > + > > + /* Set GPP Out Enable */ > > + writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); > > + writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); > > + > > + return 0; > > +} > > + > > +int board_init(void) > > +{ > > + int i; > > + > > + /* Address of boot parameters */ > > + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; > > + > > + /* Toggle GPIO41 to reset onboard switch and phy */ > > + clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); > > + clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); > > + mdelay(1); > > + setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); > > + mdelay(10); > > + > > + /* Init I2C IO expanders */ > > + for (i = 0; i < ARRAY_SIZE(io_exp); i++) > > + i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); > > + > > + return 0; > > +} > > + > > +int checkboard(void) > > +{ > > + puts("Board: SolidRun ClearFog\n"); > > + > > + return 0; > > +} > > + > > +int board_eth_init(bd_t *bis) > > +{ > > + cpu_eth_init(bis); /* Built in controller(s) come first */ > > + return pci_eth_init(bis); > > +} > > diff --git a/board/solidrun/clearfog/kwbimage.cfg > > b/board/solidrun/clearfog/kwbimage.cfg new file mode 100644 > > index 0000000..c650c2c > > --- /dev/null > > +++ b/board/solidrun/clearfog/kwbimage.cfg > > @@ -0,0 +1,12 @@ > > +# > > +# Copyright (C) 2015 Stefan Roese <s...@denx.de> > > +# > > + > > +# Armada XP uses version 1 image format > > +VERSION 1 > > + > > +# Boot Media configurations > > +BOOT_FROM sdio > > + > > +# Binary Header (bin_hdr) with DDR3 training code > > +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 > > diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig > > new file mode 100644 > > index 0000000..7e5cefe > > --- /dev/null > > +++ b/configs/clearfog_defconfig > > @@ -0,0 +1,20 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_MVEBU=y > > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > > +CONFIG_TARGET_CLEARFOG=y > > +CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" > > +CONFIG_SPL=y > > +# CONFIG_CMD_IMLS is not set > > +# CONFIG_CMD_FLASH is not set > > +CONFIG_CMD_USB=y > > +# CONFIG_CMD_SETEXPR is not set > > +CONFIG_SPI_FLASH=y > > +CONFIG_DEBUG_UART=y > > +CONFIG_DEBUG_UART_BASE=0xd0012000 > > +CONFIG_DEBUG_UART_CLOCK=250000000 > > +CONFIG_DEBUG_UART_SHIFT=2 > > +CONFIG_SYS_NS16550=y > > +CONFIG_USB=y > > +CONFIG_DM_USB=y > > +CONFIG_USB_EHCI_HCD=y > > +CONFIG_USB_STORAGE=y > > diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h > > new file mode 100644 > > index 0000000..c74415d > > --- /dev/null > > +++ b/include/configs/clearfog.h > > @@ -0,0 +1,183 @@ > > +/* > > + * Copyright (C) 2015 Stefan Roese <s...@denx.de> > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#ifndef _CONFIG_CLEARFOG_H > > +#define _CONFIG_CLEARFOG_H > > + > > +/* > > + * High Level Configuration Options (easy to change) > > + */ > > +#define CONFIG_ARMADA_XP /* SOC Family Name */ > > +#define CONFIG_ARMADA_38X > > +#define CONFIG_DB_88F6820_GP /* Board target name for DDR > > training */ > > + > > +#define CONFIG_DISPLAY_BOARDINFO_LATE > > + > > +/* > > + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed > > + * for DDR ECC byte filling in the SPL before loading the main > > + * U-Boot into it. > > + */ > > +#define CONFIG_SYS_TEXT_BASE 0x00800000 > > +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ > > + > > +/* > > + * Commands configuration > > + */ > > +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ > > +#define CONFIG_CMD_BOOTZ > > +#define CONFIG_CMD_CACHE > > +#define CONFIG_CMD_DHCP > > +#define CONFIG_CMD_ENV > > +#define CONFIG_CMD_EXT2 > > +#define CONFIG_CMD_EXT4 > > +#define CONFIG_CMD_FAT > > +#define CONFIG_CMD_FS_GENERIC > > +#define CONFIG_CMD_I2C > > +#define CONFIG_CMD_MMC > > +#define CONFIG_CMD_PCI > > +#define CONFIG_CMD_PING > > +#define CONFIG_CMD_SF > > +#define CONFIG_CMD_SPI > > +#define CONFIG_CMD_TFTPPUT > > +#define CONFIG_CMD_TIME > > + > > +/* I2C */ > > +#define CONFIG_SYS_I2C > > +#define CONFIG_SYS_I2C_MVTWSI > > +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE > > +#define CONFIG_SYS_I2C_SLAVE 0x0 > > +#define CONFIG_SYS_I2C_SPEED 100000 > > + > > +/* SPI NOR flash default params, used by sf commands */ > > +#define CONFIG_SF_DEFAULT_SPEED 1000000 > > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 > > +#define CONFIG_SPI_FLASH_STMICRO > > + > > +/* > > + * SDIO/MMC Card Configuration > > + */ > > +#define CONFIG_MMC > > +#define CONFIG_MMC_SDMA > > +#define CONFIG_GENERIC_MMC > > +#define CONFIG_SDHCI > > +#define CONFIG_MV_SDHCI > > +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE > > + > > +/* Partition support */ > > +#define CONFIG_DOS_PARTITION > > +#define CONFIG_EFI_PARTITION > > + > > +/* Additional FS support/configuration */ > > +#define CONFIG_SUPPORT_VFAT > > + > > +/* USB/EHCI configuration */ > > +#define CONFIG_EHCI_IS_TDI > > + > > +#define CONFIG_ENV_MIN_ENTRIES 128 > > + > > +/* Environment in MMC */ > > +#define CONFIG_ENV_IS_IN_MMC > > +#define CONFIG_SYS_MMC_ENV_DEV 0 > > +#define CONFIG_ENV_SECT_SIZE 0x200 > > +#define CONFIG_ENV_SIZE 0x10000 > > +/* > > + * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC > > + * boot image starts @ LBA-0. > > + * As result in MMC/eMMC case it will be a 1 sector gap between u-boot > > + * image and environment > > + */ > > +#define CONFIG_ENV_OFFSET 0xf0000 > > +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET > > + > > +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ > > +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ > > + > > +/* PCIe support */ > > +#ifndef CONFIG_SPL_BUILD > > +#define CONFIG_PCI > > +#define CONFIG_PCI_MVEBU > > +#define CONFIG_PCI_PNP > > +#define CONFIG_PCI_SCAN_SHOW > > +#endif > > + > > +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ > > startup */ > > +#define CONFIG_SYS_ALT_MEMTEST > > + > > +/* Keep device tree and initrd in lower memory so the kernel can access > > them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ > > + "fdt_high=0x10000000\0" \ > > + "initrd_high=0x10000000\0" > > + > > +/* SPL */ > > +/* > > + * Select the boot device here > > + * > > + * Currently supported are: > > + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash > > + * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) > > + */ > > +#define SPL_BOOT_SPI_NOR_FLASH 1 > > +#define SPL_BOOT_SDIO_MMC_CARD 2 > > +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD > > + > > +/* Defines for SPL */ > > +#define CONFIG_SPL_FRAMEWORK > > +#define CONFIG_SPL_SIZE (140 << 10) > > +#define CONFIG_SPL_TEXT_BASE 0x40000030 > > +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) > > + > > +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) > > +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) > > + > > +#ifdef CONFIG_SPL_BUILD > > +#define CONFIG_SYS_MALLOC_SIMPLE > > +#endif > > + > > +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) > > +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) > > + > > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > > +#define CONFIG_SPL_SERIAL_SUPPORT > > +#define CONFIG_SPL_I2C_SUPPORT > > + > > +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH > > +/* SPL related SPI defines */ > > +#define CONFIG_SPL_SPI_SUPPORT > > +#define CONFIG_SPL_SPI_FLASH_SUPPORT > > +#define CONFIG_SPL_SPI_LOAD > > +#define CONFIG_SPL_SPI_BUS 0 > > +#define CONFIG_SPL_SPI_CS 0 > > +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 > > +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS > > +#endif > > + > > +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD > > +/* SPL related MMC defines */ > > +#define CONFIG_SPL_MMC_SUPPORT > > +#define CONFIG_SPL_LIBDISK_SUPPORT > > +#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) > > +#define CONFIG_SYS_U_BOOT_OFFS > > CONFIG_SYS_MMC_U_BOOT_OFFS > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR > > ((CONFIG_SYS_U_BOOT_OFFS / > > 512)\ + + 1) > > +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB > */ > > +#ifdef CONFIG_SPL_BUILD > > +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ > > +#endif > > +#endif > > + > > +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ > > +#define CONFIG_SYS_MVEBU_DDR_A38X > > +#define CONFIG_DDR3 > > + > > +/* > > + * mv-common.h should be defined after CMD configs since it used them > > + * to enable certain macros > > + */ > > +#include "mv-common.h" > > + > > +#endif /* _CONFIG_CLEARFOG_H */ > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
