This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng <bmeng...@gmail.com>

---

 arch/x86/dts/Makefile                     |  1 +
 arch/x86/dts/cougarcanyon2.dts            | 96 +++++++++++++++++++++++++++++++
 board/intel/Kconfig                       |  9 +++
 board/intel/cougarcanyon2/Kconfig         | 25 ++++++++
 board/intel/cougarcanyon2/MAINTAINERS     |  6 ++
 board/intel/cougarcanyon2/Makefile        |  7 +++
 board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++
 board/intel/cougarcanyon2/start.S         |  9 +++
 configs/cougarcanyon2_defconfig           | 21 +++++++
 include/configs/cougarcanyon2.h           | 34 +++++++++++
 10 files changed, 256 insertions(+)
 create mode 100644 arch/x86/dts/cougarcanyon2.dts
 create mode 100644 board/intel/cougarcanyon2/Kconfig
 create mode 100644 board/intel/cougarcanyon2/MAINTAINERS
 create mode 100644 board/intel/cougarcanyon2/Makefile
 create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c
 create mode 100644 board/intel/cougarcanyon2/start.S
 create mode 100644 configs/cougarcanyon2_defconfig
 create mode 100644 include/configs/cougarcanyon2.h

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 64e5694..84feb19 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -5,6 +5,7 @@
 dtb-y += bayleybay.dtb \
        chromebook_link.dtb \
        chromebox_panther.dtb \
+       cougarcanyon2.dtb \
        crownbay.dtb \
        efi.dtb \
        galileo.dtb \
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
new file mode 100644
index 0000000..486999e
--- /dev/null
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng...@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+       model = "Intel Cougar Canyon 2";
+       compatible = "intel,cougarcanyon2", "intel,chiefriver";
+
+       aliases {
+               spi0 = "/spi";
+       };
+
+       config {
+               silent_console = <0>;
+       };
+
+       chosen {
+               stdout-path = "/serial";
+       };
+
+       microcode {
+               update@0 {
+#include "microcode/m12306a2_00000008.dtsi"
+               };
+               update@1 {
+#include "microcode/m12306a4_00000007.dtsi"
+               };
+               update@2 {
+#include "microcode/m12306a5_00000007.dtsi"
+               };
+               update@3 {
+#include "microcode/m12306a8_00000010.dtsi"
+               };
+               update@4 {
+#include "microcode/m12306a9_0000001b.dtsi"
+               };
+       };
+
+       fsp {
+               compatible = "intel,ivybridge-fsp";
+               fsp,enable-ht;
+       };
+
+       pci {
+               #address-cells = <3>;
+               #size-cells = <2>;
+               compatible = "pci-x86";
+               u-boot,dm-pre-reloc;
+               ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+                         0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+                         0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+       };
+
+       gpioa {
+               compatible = "intel,ich6-gpio";
+               u-boot,dm-pre-reloc;
+               reg = <0 0x10>;
+               bank-name = "A";
+       };
+
+       gpiob {
+               compatible = "intel,ich6-gpio";
+               u-boot,dm-pre-reloc;
+               reg = <0x30 0x10>;
+               bank-name = "B";
+       };
+
+       gpioc {
+               compatible = "intel,ich6-gpio";
+               u-boot,dm-pre-reloc;
+               reg = <0x40 0x10>;
+               bank-name = "C";
+       };
+
+       spi {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "intel,ich-spi";
+               spi-flash@0 {
+                       reg = <0>;
+                       compatible = "winbond,w25q64bv", "spi-flash";
+                       memory-map = <0xff800000 0x00800000>;
+               };
+       };
+
+};
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
index f7d71c3..4d341aa 100644
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY
          4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
          PCIe and some other sensor interfaces.
 
+config TARGET_COUGARCANYON2
+       bool "Cougar Canyon 2"
+       help
+         This is the Intel Cougar Canyon 2 Customer Reference Board. It
+         is built on the Chief River platform with Intel Ivybridge Processor
+         and Panther Point chipset. The board has 4GB RAM, with some other
+         peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
+
 config TARGET_CROWNBAY
        bool "Crown Bay"
        help
@@ -54,6 +62,7 @@ config TARGET_MINNOWMAX
 endchoice
 
 source "board/intel/bayleybay/Kconfig"
+source "board/intel/cougarcanyon2/Kconfig"
 source "board/intel/crownbay/Kconfig"
 source "board/intel/galileo/Kconfig"
 source "board/intel/minnowmax/Kconfig"
diff --git a/board/intel/cougarcanyon2/Kconfig 
b/board/intel/cougarcanyon2/Kconfig
new file mode 100644
index 0000000..95a617b
--- /dev/null
+++ b/board/intel/cougarcanyon2/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_COUGARCANYON2
+
+config SYS_BOARD
+       default "cougarcanyon2"
+
+config SYS_VENDOR
+       default "intel"
+
+config SYS_SOC
+       default "ivybridge"
+
+config SYS_CONFIG_NAME
+       default "cougarcanyon2"
+
+config SYS_TEXT_BASE
+       default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select X86_RESET_VECTOR
+       select NORTHBRIDGE_INTEL_IVYBRIDGE
+       select HAVE_FSP
+       select BOARD_ROMSIZE_KB_2048
+
+endif
diff --git a/board/intel/cougarcanyon2/MAINTAINERS 
b/board/intel/cougarcanyon2/MAINTAINERS
new file mode 100644
index 0000000..a486739
--- /dev/null
+++ b/board/intel/cougarcanyon2/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL COUGAR CANYON 2 BOARD
+M:     Bin Meng <bmeng...@gmail.com>
+S:     Maintained
+F:     board/intel/cougarcanyon2/
+F:     include/configs/cougarcanyon2.h
+F:     configs/cougarcanyon2_defconfig
diff --git a/board/intel/cougarcanyon2/Makefile 
b/board/intel/cougarcanyon2/Makefile
new file mode 100644
index 0000000..807f284
--- /dev/null
+++ b/board/intel/cougarcanyon2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng...@gmail.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += cougarcanyon2.o start.o
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c 
b/board/intel/cougarcanyon2/cougarcanyon2.c
new file mode 100644
index 0000000..4cc47fb
--- /dev/null
+++ b/board/intel/cougarcanyon2/cougarcanyon2.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng...@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ibmpc.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <pci.h>
+#include <smsc_sio1007.h>
+
+#define SIO1007_RUNTIME_IOPORT 0x180
+
+int board_early_init_f(void)
+{
+       /* Initialize LPC interface to turn on superio chipset decode range */
+       x86_pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC,
+                              COMA_DEC_RANGE | COMB_DEC_RANGE);
+       x86_pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
+       x86_pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
+                              (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
+       x86_pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
+                              SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
+
+       /* Enable legacy serial port at 0x3f8 */
+       sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
+
+       /* Enable SIO1007 runtime I/O port at 0x180 */
+       sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
+
+       /*
+        * On Cougar Canyon 2 board, the RS232 transiver connected to serial
+        * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
+        * Set the pin value to 1 to enable the RS232 transiver.
+        */
+       sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
+                           GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
+       sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
+
+       return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+       return;
+}
diff --git a/board/intel/cougarcanyon2/start.S 
b/board/intel/cougarcanyon2/start.S
new file mode 100644
index 0000000..a71db69
--- /dev/null
+++ b/board/intel/cougarcanyon2/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng...@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+       jmp     early_board_init_ret
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
new file mode 100644
index 0000000..2d23dc3
--- /dev/null
+++ b/configs/cougarcanyon2_defconfig
@@ -0,0 +1,21 @@
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
+CONFIG_TARGET_COUGARCANYON2=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
new file mode 100644
index 0000000..faac552
--- /dev/null
+++ b/include/configs/cougarcanyon2.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng...@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN         (2 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SMSC_SIO1007
+
+#define CONFIG_PCI_PNP
+
+#define CONFIG_STD_DEVICES_SETTINGS    "stdin=serial,i8042-kbd,usbkbd\0" \
+                                       "stdout=serial,vga\0" \
+                                       "stderr=serial,vga\0"
+
+#define CONFIG_SCSI_DEV_LIST           \
+       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE           0x1000
+#define CONFIG_ENV_OFFSET              0x5ff000
+
+/* Video is not supported for now */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+#endif /* __CONFIG_H */
-- 
1.8.2.1

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