Hi Simon,
On Tue, Dec 1, 2015 at 12:11 PM, Simon Glass <s...@chromium.org> wrote:
> At some point we may need to distinguish between different types of PCHs,
> but for existing supported platforms we only need to worry about version 7
> and version 9 bridges. Add a driver for the PCH9.
>
> Signed-off-by: Simon Glass <s...@chromium.org>
> ---
>
> drivers/pch/Makefile | 1 +
> drivers/pch/pch9.c | 41 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
> create mode 100644 drivers/pch/pch9.c
>
> diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
> index 33aa727..dde9e86 100644
> --- a/drivers/pch/Makefile
> +++ b/drivers/pch/Makefile
> @@ -4,3 +4,4 @@
>
> obj-y += pch-uclass.o
> obj-y += pch7.o
> +obj-y += pch9.o
> diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
> new file mode 100644
> index 0000000..2f40a6b
> --- /dev/null
> +++ b/drivers/pch/pch9.c
> @@ -0,0 +1,41 @@
> +/*
> + * Copyright (C) 2014 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <pch.h>
> +
> +static int baytrail_pch_get_sbase(struct udevice *dev, ulong *sbasep)
Can we rename this to: pch9_get_sbase()?
> +{
> + uint32_t sbase_addr;
> +
> + dm_pci_read_config32(dev, 0x54, &sbase_addr);
Please #define 0x54.
> + *sbasep = sbase_addr & 0xfffffe00;
> +
> + return 0;
> +}
> +
> +static int baytrail_pch_get_version(struct udevice *dev)
pch9_get_version()
> +{
> + return 9;
> +}
> +
> +static const struct pch_ops baytrail_pch_ops = {
pch9_ops
> + .get_sbase = baytrail_pch_get_sbase,
> + .get_version = baytrail_pch_get_version,
> +};
> +
> +static const struct udevice_id baytrailpch_ids[] = {
pch9_ids
> + { .compatible = "intel,pch9" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pch9_drv) = {
> + .name = "intel-pch",
"intel-pch9"
> + .id = UCLASS_PCH,
> + .of_match = baytrailpch_ids,
> + .ops = &baytrail_pch_ops,
> +};
> --
Regards,
Bin
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