SDRAM doesn't always start at 0. Adjust the region mapping so that it works
on platforms where SDRAM is somewhere else.
This needs testing on other platforms.
Signed-off-by: Simon Glass <s...@chromium.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Rename 'addr' to 'size'
- Correct logic for use of gd->pci_ram_top
drivers/pci/pci-uclass.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 1d93194..6d860c4 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -680,8 +680,8 @@ static int decode_regions(struct pci_controller *hose,
const void *blob,
int parent_node, int node)
{
int pci_addr_cells, addr_cells, size_cells;
+ phys_addr_t base = 0, size;
int cells_per_record;
- phys_addr_t addr;
const u32 *prop;
int len;
int i;
@@ -732,11 +732,14 @@ static int decode_regions(struct pci_controller *hose,
const void *blob,
}
/* Add a region for our local memory */
- addr = gd->ram_size;
- if (gd->pci_ram_top && gd->pci_ram_top < addr)
- addr = gd->pci_ram_top;
- pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ size = gd->ram_size;
+#ifdef CONFIG_SYS_SDRAM_BASE
+ base = CONFIG_SYS_SDRAM_BASE;
+#endif
+ if (gd->pci_ram_top && gd->pci_ram_top < base + size)
+ size = gd->pci_ram_top - base;
+ pci_set_region(hose->regions + hose->region_count++, base, base,
+ size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
return 0;
}
--
2.6.0.rc2.230.g3dd15c0
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