Hi all,
I see that miiphybb.c driver is used only with PPC architecture yet.
I would like to use it with ARM. Would be it reasonable to make this
driver arch independent? I have small patch and it changes defined ports
and pins with function calls, which should be provided by each CPU. I
attached this patch for RFC. If it is suitable, I may need help with
changing all > 20 PPC boards using this driver, because I don't have
experience with PPC. Would be there some volunteers willing to help? Or
please suggest other solution to make optimize this driver.
Regards,
Darius A.
Make miiphybb gpio interface more flexible
From: Darius Augulis <augulis.dar...@gmail.com>
Signed-off-by: Darius Augulis <augulis.dar...@gmail.com>
---
drivers/net/phy/miiphybb.c | 116 ++++++++++++++++++++------------------------
drivers/net/phy/miiphybb.h | 22 ++++++++
2 files changed, 75 insertions(+), 63 deletions(-)
create mode 100644 drivers/net/phy/miiphybb.h
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index b77c917..08d0a80 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -27,8 +27,7 @@
*/
#include <common.h>
-#include <ioports.h>
-#include <ppc_asm.tmpl>
+#include "miiphybb.h"
/*****************************************************************************
*
@@ -38,9 +37,6 @@
static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
-#endif
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
@@ -50,61 +46,61 @@ static void miiphy_pre (char read, unsigned char addr,
unsigned char reg)
* but it is safer and will be much more robust.
*/
- MDIO_ACTIVE;
- MDIO (1);
+ mii_mdio_active(1);
+ mii_mdio_set(1);
for (j = 0; j < 32; j++) {
- MDC (0);
+ mii_mdc_set(0);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
}
/* send the start bit (01) and the read opcode (10) or write (10) */
- MDC (0);
- MDIO (0);
+ mii_mdc_set(0);
+ mii_mdio_set(0);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
- MDC (0);
- MDIO (1);
+ mii_mdc_set(0);
+ mii_mdio_set(1);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
- MDC (0);
- MDIO (read);
+ mii_mdc_set(0);
+ mii_mdio_set(read);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
- MDC (0);
- MDIO (!read);
+ mii_mdc_set(0);
+ mii_mdio_set(!read);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
/* send the PHY address */
for (j = 0; j < 5; j++) {
- MDC (0);
+ mii_mdc_set(0);
if ((addr & 0x10) == 0) {
- MDIO (0);
+ mii_mdio_set(0);
} else {
- MDIO (1);
+ mii_mdio_set(1);
}
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
addr <<= 1;
}
/* send the register address */
for (j = 0; j < 5; j++) {
- MDC (0);
+ mii_mdc_set(0);
if ((reg & 0x10) == 0) {
- MDIO (0);
+ mii_mdio_set(0);
} else {
- MDIO (1);
+ mii_mdio_set(1);
}
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
reg <<= 1;
}
@@ -123,31 +119,28 @@ int bb_miiphy_read (char *devname, unsigned char addr,
{
short rdreg; /* register working value */
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
-#endif
if (value == NULL) {
puts("NULL value pointer\n");
return (-1);
}
- miiphy_pre (1, addr, reg);
+ miiphy_pre(1, addr, reg);
/* tri-state our MDIO I/O pin so we can read */
- MDC (0);
- MDIO_TRISTATE;
+ mii_mdc_set(0);
+ mii_mdio_active(0);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
/* check the turnaround bit: the PHY should be driving it to zero */
- if (MDIO_READ != 0) {
+ if (mii_mdio_read() != 0) {
/* puts ("PHY didn't drive TA low\n"); */
for (j = 0; j < 32; j++) {
- MDC (0);
+ mii_mdc_set(0);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
}
/* There is no PHY, set value to 0xFFFF and return */
@@ -155,25 +148,25 @@ int bb_miiphy_read (char *devname, unsigned char addr,
return (-1);
}
- MDC (0);
+ mii_mdc_set(0);
MIIDELAY;
/* read 16 bits of register data, MSB first */
rdreg = 0;
for (j = 0; j < 16; j++) {
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
rdreg <<= 1;
- rdreg |= MDIO_READ;
- MDC (0);
+ rdreg |= mii_mdio_read();
+ mii_mdc_set(0);
MIIDELAY;
}
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
- MDC (0);
+ mii_mdc_set(0);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
*value = rdreg;
@@ -197,34 +190,31 @@ int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
-#endif
- miiphy_pre (0, addr, reg);
+ miiphy_pre(0, addr, reg);
/* send the turnaround (10) */
- MDC (0);
- MDIO (1);
+ mii_mdc_set(0);
+ mii_mdio_set(1);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
- MDC (0);
- MDIO (0);
+ mii_mdc_set(0);
+ mii_mdio_set(0);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
/* write 16 bits of register data, MSB first */
for (j = 0; j < 16; j++) {
- MDC (0);
+ mii_mdc_set(0);
if ((value & 0x00008000) == 0) {
- MDIO (0);
+ mii_mdio_set(0);
} else {
- MDIO (1);
+ mii_mdio_set(1);
}
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
value <<= 1;
}
@@ -232,10 +222,10 @@ int bb_miiphy_write (char *devname, unsigned char addr,
/*
* Tri-state the MDIO line.
*/
- MDIO_TRISTATE;
- MDC (0);
+ mii_mdio_active(0);
+ mii_mdc_set(0);
MIIDELAY;
- MDC (1);
+ mii_mdc_set(1);
MIIDELAY;
return 0;
diff --git a/drivers/net/phy/miiphybb.h b/drivers/net/phy/miiphybb.h
new file mode 100644
index 0000000..89eacb1
--- /dev/null
+++ b/drivers/net/phy/miiphybb.h
@@ -0,0 +1,22 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <daugu...@linkodas.com> <augulis.dar...@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _MIIPHYBB_H
+#define _MIIPHYBB_H
+
+extern inline void mii_mdio_active(unsigned char x);
+extern inline void mii_mdio_set(unsigned char x);
+extern inline void mii_mdc_set(unsigned char x);
+extern inline unsigned char mii_mdio_read(void);
+
+#endif
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