Hello Stephen,
On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren
<swar...@wwwdotorg.org> wrote:
> On 10/05/2015 12:08 PM, Stephen Warren wrote:
> > From: Stephen Warren <swar...@nvidia.com>
> >
> > The implementation of noncached_init() uses define MMU_SECTION_SIZE.
> > Define this on ARM64.
> >
> > Move the prototype of noncached_{init,alloc}() to a location that
> > doesn't depend on !defined(CONFIG_ARM64).
> >
> > Note that noncached_init() calls mmu_set_region_dcache_behaviour() which
> > relies on something having set up translation tables with 2MB block size.
> > The core ARMv8 MMU setup code does not do this by default, but currently
> > relies on SoC specific MMU setup code. Be aware of this before enabling
> > this feature on your platform!
>
> Albert, it looks like I forgot to add you to the CC on this email.
> Sorry! Could you please take a look at this series and tell me what you
> think? If you need a resend just let me know.
>
> Also note that this series is a dependency for PCIe support on 64-bit
> Tegra systems; I guess either Tom Warren would be looking for an ack so
> he can apply the series to the Tegra tree, or perhaps if you just apply
> the whole series, he can base his branch on the branch where you apply this.
I'll have a look at it in the coming days.
Amicalement,
--
Albert.
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