Hi there,
i am currently debugging on my zynq zc702 board and therefore i have to
study the qspi-driver :-)
i've some questions about the implementation details.
On 01.09.2015 08:11, Jagan Teki wrote:
Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.
(....)
+static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
+{
+ u32 data = 0;
+ u32 fifocount = 0;
+ unsigned len, offset;
+ struct zynq_qspi_regs *regs = priv->regs;
+ static const unsigned offsets[4] = {
+ ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
+ ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
+
+ while ((fifocount < size) &&
+ (priv->bytes_to_transfer > 0)) {
+ if (priv->bytes_to_transfer >= 4) {
+ if (priv->tx_buf) {
+ memcpy(&data, priv->tx_buf, 4);
+ priv->tx_buf += 4;
+ } else {
+ data = 0;
+ }
+ writel(data, ®s->txd0r);
+ priv->bytes_to_transfer -= 4;
+ fifocount++;
+ } else {
+ /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
+ if (!(readl(®s->isr)
+ & ZYNQ_QSPI_IXR_TXOW_MASK) &&
+ !priv->rx_buf)
+ return;
+ len = priv->bytes_to_transfer;
+ zynq_qspi_write_data(priv, &data, len);
+ offset = (priv->rx_buf) ? offsets[0] : offsets[len];
+ writel(data, ®s->cr + (offset / 4));
I do not understand "offset / 4", if priv->rx_buf == NULL we have an
offset of 0x1C / 4 --> 7, this end in a write to an unaligned register
address.
What is the purpose of this ?
+ }
+ }
+}
+
best regards,
Hannes
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