On Friday, October 09, 2015 at 10:00:26 AM, Thomas Chou wrote: > Hi Marek, > > On 10/09/2015 10:49 AM, Ley Foon Tan wrote: > >> Is this an attempt at poor-mans' rounding ? I think you want to implment > >> something like arch/arm/cpu/arm926ejs/cache.c check_cache_range() and > >> NOT do any rounding here. The reason for that is that if you do > >> rounding, you might accidentally corrupt a piece of memory which was > >> just delivered via DMA before you did the flush. > > > > The code above is to convert the address to dcache line size. > > arch/arm/cpu/arm926ejs/cache.c check_cache_range() will skip the cache > > flushing if it is unaligned to cache line size. I'm not sure how > > frequent U-boot access to non-aligned cache line size. > > Thanks a lot for your looking into this, Ley Foon. > > I think we take cache flushing in a different way to arm926ejs. > > In nios2 driver programming, we would request all the DMA buffers be > aligned to cache line. This is necessary to avoid the cache racing issue > as you mention above.
This is what ARM does as well. > In nios2, we don't skip the flushing when the inputs are not aligned > like that of arm926ejs. We always flush all cache lines in the range, > even if a single byte to flush is in request. So the inputs are rounded > to get the lower and upper cache lines range inside the cache flush > functions. The caller need not be aware of the detail. This is incorrect and all the places which produce these unaligned cache operations must be fixed. > In the copy_exception_trampoline() patch, both dcache and icache must be > flushed at the exception target address. Though the flush range is only > 12 bytes, which won't be aligned. > > Thank you for your review. > > Best regards, > Thomas Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
