PCI driver currently hangs on mx6qp.
Toggle the reset bit with the appropriate timings to fix the issue.
Based on the FSL kernel driver implementation.
Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
---
arch/arm/include/asm/arch-mx6/iomux.h | 2 ++
drivers/pci/pcie_imx.c | 14 ++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h
b/arch/arm/include/asm/arch-mx6/iomux.h
index 9b3a91f..e3ef59f 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -18,6 +18,8 @@
#define IOMUXC_GPR1_REF_SSP_EN (1 << 16)
#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
+#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29)
+
/*
* IOMUXC_GPR5 bit fields
*/
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 1568f20..ddfe389 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -19,6 +19,7 @@
#include <asm/io.h>
#include <linux/sizes.h>
#include <errno.h>
+#include <asm/arch/sys_proto.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
@@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller
*hose, pci_dev_t d,
static int imx6_pcie_assert_core_reset(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ if (is_mx6dqp())
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
#if defined(CONFIG_MX6SX)
struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
@@ -542,6 +547,15 @@ static int imx6_pcie_deassert_core_reset(void)
*/
mdelay(50);
+ if (is_mx6dqp()) {
+ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+ /*
+ * some delay is required by 6qp, after the SW_RST is
+ * cleared and before accessing the cfg register.
+ */
+ udelay(200);
+ }
+
#if defined(CONFIG_MX6SX)
/* SSP_EN is not used on MX6SX anymore */
clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
--
1.9.1
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